NXP Semiconductors LPC13xx 2024.06.02 LPC1311/13/42/43 32-bit ARM Cortex-M3 microcontroller up to 32 kB flash and 8 kB SRAM USB device CM3 r0p0 little 3 false 8 32 ADC Analog-to-Digital Converter (ADC) ADC 0x0 0x0 0xFFF registers n ADC 49 CR A/D Control Register. The AD0CR register must be written to select the operating mode before A/D conversion can occur. 0x0 read-write n 0x0 0x0 BURST Burst select 16 17 ENUM SOFTWARE_CONTROLLED_ Software-controlled mode: Conversions are software-controlled and require 11 clocks. 0 HARDWARE_SCAN_MODE_ Hardware scan mode: The AD converter does repeated conversions at the rate selected by the CLKS field, scanning (if necessary) through the pins selected by 1s in the SEL field. The first conversion after the start corresponds to the least-significant bit set to 1 in the SEL field, then the next higher bits (pins) set to 1 are scanned if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion in progress when this bit is cleared will be completed. Important: START bits must be 000 when BURST = 1 or conversions will not start. 1 CLKDIV The APB clock (PCLK) is divided by CLKDIV +1 to produce the clock for the ADC, which should be less than or equal to 4.5 MHz. Typically, software should program the smallest value in this field that yields a clock of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable. 8 16 CLKS This field selects the number of clocks used for each conversion in Burst mode, and the number of bits of accuracy of the result in the LS bits of ADDR, between 11 clocks (10 bits) and 4 clocks (3 bits). 17 20 ENUM 11_CLOCKS_/_10_BITS 11 clocks / 10 bits 0x0 11_CLOCKS 11 clocks / 10 bits 0x0 10_CLOCKS_/_9_BITS 10 clocks / 9 bits 0x1 10_CLOCKS 10 clocks / 9 bits 0x1 9_CLOCKS_/_8_BITS 9 clocks / 8 bits 0x2 9_CLOCKS 9 clocks / 8 bits 0x2 8_CLOCKS_/_7_BITS 8 clocks / 7 bits 0x3 8_CLOCKS 8 clocks / 7 bits 0x3 7_CLOCKS_/_6_BITS 7 clocks / 6 bits 0x4 7_CLOCKS 7 clocks / 6 bits 0x4 6_CLOCKS_/_5_BITS 6 clocks / 5 bits 0x5 6_CLOCKS 6 clocks / 5 bits 0x5 5_CLOCKS_/_4_BITS 5 clocks / 4 bits 0x6 5_CLOCKS 5 clocks / 4 bits 0x6 4_CLOCKS_/_3_BITS 4 clocks / 3 bits 0x7 4_CLOCKS 4 clocks / 3 bits 0x7 EDGE This bit is significant only when the START field contains 010-111. In these cases: 27 28 ENUM RISING Start conversion on a rising edge on the selected CAP/MAT signal. 0 FALLING Start conversion on a falling edge on the selected CAP/MAT signal. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 28 32 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 28 32 SEL Selects which of the AD7:0 pins is (are) to be sampled and converted. Bit 0 selects Pin AD0, bit 1 selects pin AD1,..., and bit 7 selects pin AD7. In software-controlled mode (BURST = 0), only one channel can be selected, i.e. only one of these bits should be 1. In hardware scan mode (BURST = 1), any numbers of channels can be selected, i.e any or all bits can be set to 1. If all bits are set to 0, channel 0 is selected automatically (SEL = 0x01). 0 8 START When the BURST bit is 0, these bits control whether and when an A/D conversion is started: 24 27 ENUM NO_START_THIS_VALUE No start (this value should be used when clearing PDN to 0). 0x0 NOW Start conversion now. 0x1 EDGEPIO0_2 Start conversion when the edge selected by bit 27 occurs on PIO0_2/SSEL/CT16B0_CAP0. 0x2 EDGEPIO1_5 Start conversion when the edge selected by bit 27 occurs on PIO1_5/DIR/CT32B0_CAP0. 0x3 EDGE CT32B0_MAT0 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0. Timer match function does not need to be selected on the device pin. 0x4 EDGECT32B0_MAT0 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0. Timer match function does not need to be selected on the device pin. 0x4 EDGE CT32B1_MAT0 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1. Timer match function does not need to be selected on the device pin. 0x5 EDGECT32B1_MAT0 Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1. Timer match function does not need to be selected on the device pin. 0x5 EDGE CT16B0_MAT0 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0. Timer match function does not need to be selected on the device pin. 0x6 EDGE CT16B0_MAT0 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0. Timer match function does not need to be selected on the device pin. 0x6 EDGECT16B0_MAT0 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1. Timer match function does not need to be selected on the device pin. 0x7 EDGECT16B0_MAT0 Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1. Timer match function does not need to be selected on the device pin. 0x7 DR0 A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n 0x10 -1 read-write n 0x0 0x0 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. 31 32 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. 30 31 RESERVED Reserved. 16 30 RESERVED Reserved. 16 30 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. 6 16 DR1 A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n 0x14 -1 read-write n 0x0 0x0 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. 31 32 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. 30 31 RESERVED Reserved. 16 30 RESERVED Reserved. 16 30 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. 6 16 DR2 A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n 0x18 -1 read-write n 0x0 0x0 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. 31 32 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. 30 31 RESERVED Reserved. 16 30 RESERVED Reserved. 16 30 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. 6 16 DR3 A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n 0x1C -1 read-write n 0x0 0x0 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. 31 32 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. 30 31 RESERVED Reserved. 16 30 RESERVED Reserved. 16 30 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. 6 16 DR4 A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n 0x20 -1 read-write n 0x0 0x0 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. 31 32 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. 30 31 RESERVED Reserved. 16 30 RESERVED Reserved. 16 30 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. 6 16 DR5 A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n 0x24 -1 read-write n 0x0 0x0 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. 31 32 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. 30 31 RESERVED Reserved. 16 30 RESERVED Reserved. 16 30 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. 6 16 DR6 A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n 0x28 -1 read-write n 0x0 0x0 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. 31 32 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. 30 31 RESERVED Reserved. 16 30 RESERVED Reserved. 16 30 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. 6 16 DR7 A/D Channel n Data Register. This register contains the result of the most recent conversion completed on channel n 0x2C -1 read-write n 0x0 0x0 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read. 31 32 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits.This bit is cleared by reading this register. 30 31 RESERVED Reserved. 16 30 RESERVED Reserved. 16 30 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin, divided by the voltage on the VREF pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VREF, while 0x3FF indicates that the voltage on AD input was close to, equal to, or greater than that on VREF. 6 16 GDR A/D Global Data Register. Contains the result of the most recent A/D conversion. 0x4 read-write n 0x0 0x0 CHN These bits contain the channel from which the V_VREF bits were converted. 24 27 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started. 31 32 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits. 30 31 RESERVED Reserved. 27 30 RESERVED Reserved. 16 24 RESERVED Reserved. 27 30 V_VREF When DONE is 1, this field contains a binary fraction representing the voltage on the ADn pin selected by the SEL field, divided by the voltage on the VDD pin. Zero in the field indicates that the voltage on the ADn pin was less than, equal to, or close to that on VSS, while 0x3FF indicates that the voltage on ADn was close to, equal to, or greater than that on VREF. 6 16 INTEN A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt. 0xC read-write n 0x0 0x0 ADGINTEN When 1, enables the global DONE flag in ADDR to generate an interrupt. When 0, only the individual A/D channels enabled by ADINTEN 7:0 will generate interrupts. 8 9 ADINTEN0 These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc. 0 1 ADINTEN1 These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc. 1 2 ADINTEN2 These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc. 2 3 ADINTEN3 These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc. 3 4 ADINTEN4 These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc. 4 5 ADINTEN5 These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc. 5 6 ADINTEN6 These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc. 6 7 ADINTEN7 These bits allow control over which A/D channels generate interrupts for conversion completion. When bit 0 is one, completion of a conversion on A/D channel 0 will generate an interrupt, when bit 1 is one, completion of a conversion on A/D channel 1 will generate an interrupt, etc. 7 8 RESERVED Reserved. 9 32 STAT A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt flag. 0x30 read-only n 0x0 0x0 ADINT This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register. 16 17 DONE0 These bits mirror the DONE status flags that appear in the result register for each A/D channel. 0 1 DONE1 These bits mirror the DONE status flags that appear in the result register for each A/D channel. 1 2 DONE2 These bits mirror the DONE status flags that appear in the result register for each A/D channel. 2 3 DONE3 These bits mirror the DONE status flags that appear in the result register for each A/D channel. 3 4 DONE4 These bits mirror the DONE status flags that appear in the result register for each A/D channel. 4 5 DONE5 These bits mirror the DONE status flags that appear in the result register for each A/D channel. 5 6 DONE6 These bits mirror the DONE status flags that appear in the result register for each A/D channel. 6 7 DONE7 These bits mirror the DONE status flags that appear in the result register for each A/D channel. 7 8 OVERRUN0 These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously. 8 9 OVERRUN1 These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously. 9 10 OVERRUN2 These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously. 10 11 OVERRUN3 These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously. 11 12 OVERRUN4 These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously. 12 13 OVERRUN5 These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously. 13 14 OVERRUN6 These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously. 14 15 OVERRUN7 These bits mirror the OVERRRUN status flags that appear in the result register for each A/D channel. Reading ADSTAT allows checking the status of all A/D channels simultaneously. 15 16 RESERVED Reserved. 17 32 CT16B0 16-bit counter/timers (CT16B0/1) CT16B0 0x0 0x0 0xFFF registers n CT16B0 41 BCCR Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x28 read-write n 0x0 0x0 CAP0FE Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0I Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0RE Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 3 32 BCR0 Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input. 0x2C read-only n 0x0 0x0 CAP Timer counter capture value. 0 16 RESERVED Reserved. 16 32 BCTCR Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x70 read-write n 0x0 0x0 CIS Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. 2 4 ENUM CT16BN_CAP0 CT16Bn_CAP0 0x0 CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). 0 2 ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTHEDGES Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 BEMR External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0]. 0x3C read-write n 0x0 0x0 EM0 External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 0 1 EM1 External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 1 2 EM2 External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 2 3 EM3 External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers. 3 4 EMC0 External Match Control 0. Determines the functionality of External Match 0. 4 6 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. 6 8 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. 8 10 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. 10 12 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 BIR Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. 0x0 read-write n 0x0 0x0 CR0INT Interrupt flag for capture channel 0 event. 4 5 MR0INT Interrupt flag for match channel 0. 0 1 MR1INT Interrupt flag for match channel 1. 1 2 MR2INT Interrupt flag for match channel 2. 2 3 MR3INT Interrupt flag for match channel 3. 3 4 RESERVED Reserved 5 32 BMCR Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x14 read-write n 0x0 0x0 MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0R Reset on MR0: the TC will be reset if MR0 matches it. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 3 4 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1R Reset on MR1: the TC will be reset if MR1 matches it. 4 5 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 5 6 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 6 7 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2R Reset on MR2: the TC will be reset if MR2 matches it. 7 8 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 8 9 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 9 10 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3R Reset on MR3: the TC will be reset if MR3 matches it. 10 11 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 11 12 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 BMR0 Match Register 0 (MR0). MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x30 read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 BMR1 Match Register 0 (MR0). MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x4C read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 BMR2 Match Register 0 (MR0). MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x6C read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 BMR3 Match Register 0 (MR0). MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x90 read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 BPC Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x10 read-write n 0x0 0x0 PC Prescale counter value. 0 16 RESERVED Reserved. 16 32 BPR Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0xC read-write n 0x0 0x0 PR Prescale max value. 0 16 RESERVED Reserved. 16 32 BPWMC PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0]. 0x74 read-write n 0x0 0x0 PWMEN0 PWM channel0 enable 0 1 ENUM EM0 CT16Bn_MAT0 is controlled by EM0. 0 PWM PWM mode is enabled for CT16Bn_MAT0. 1 PWMEN1 PWM channel1 enable 1 2 ENUM EM1 CT16Bn_MAT1 is controlled by EM1. 0 PWM PWM mode is enabled for CT16Bn_MAT1. 1 PWMEN2 PWM channel2 enable 2 3 ENUM EM2 Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1. 0 PWM PWM mode is enabled for match channel 2 or pin CT16B0_MAT2. 1 PWMEN3 PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out. 3 4 ENUM EM3 Match channel 3 match channel 3 is controlled by EM3. 0 PWM PWM mode is enabled for match channel 3match channel 3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 BTC Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x8 read-write n 0x0 0x0 RESERVED Reserved. 16 32 TC Timer counter value. 0 16 BTCR Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x4 read-write n 0x0 0x0 CEN When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. 0 1 CRESET When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 2 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 2 32 CCR Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x28 read-write n 0x0 0x0 CAP0FE Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0I Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0RE Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 3 32 CR0 Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input. 0x2C read-only n 0x0 0x0 CAP Timer counter capture value. 0 16 RESERVED Reserved. 16 32 CTCR Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x70 read-write n 0x0 0x0 CIS Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. 2 4 ENUM CT16BN_CAP0 CT16Bn_CAP0 0x0 CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). 0 2 ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTHEDGES Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 EMR External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0]. 0x3C read-write n 0x0 0x0 EM0 External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 0 1 EM1 External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 1 2 EM2 External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 2 3 EM3 External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers. 3 4 EMC0 External Match Control 0. Determines the functionality of External Match 0. 4 6 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. 6 8 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. 8 10 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. 10 12 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 IR Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. 0x0 read-write n 0x0 0x0 CR0INT Interrupt flag for capture channel 0 event. 4 5 MR0INT Interrupt flag for match channel 0. 0 1 MR1INT Interrupt flag for match channel 1. 1 2 MR2INT Interrupt flag for match channel 2. 2 3 MR3INT Interrupt flag for match channel 3. 3 4 RESERVED Reserved 5 32 MCR Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x14 read-write n 0x0 0x0 MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0R Reset on MR0: the TC will be reset if MR0 matches it. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 3 4 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1R Reset on MR1: the TC will be reset if MR1 matches it. 4 5 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 5 6 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 6 7 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2R Reset on MR2: the TC will be reset if MR2 matches it. 7 8 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 8 9 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 9 10 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3R Reset on MR3: the TC will be reset if MR3 matches it. 10 11 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 11 12 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 MR0 Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x18 -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 MR1 Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x1C -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 MR2 Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x20 -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 MR3 Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x24 -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 PC Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x10 read-write n 0x0 0x0 PCVAL Prescale counter value. 0 16 RESERVED Reserved. 16 32 PR Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0xC read-write n 0x0 0x0 PRVAL Prescale max value. 0 16 RESERVED Reserved. 16 32 PWMC PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0]. 0x74 read-write n 0x0 0x0 PWMEN0 PWM channel0 enable 0 1 ENUM EM0 CT16Bn_MAT0 is controlled by EM0. 0 PWM PWM mode is enabled for CT16Bn_MAT0. 1 PWMEN1 PWM channel1 enable 1 2 ENUM EM1 CT16Bn_MAT1 is controlled by EM1. 0 PWM PWM mode is enabled for CT16Bn_MAT1. 1 PWMEN2 PWM channel2 enable 2 3 ENUM EM2 Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1. 0 PWM PWM mode is enabled for match channel 2 or pin CT16B0_MAT2. 1 PWMEN3 PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out. 3 4 ENUM EM3 Match channel 3 match channel 3 is controlled by EM3. 0 PWM PWM mode is enabled for match channel 3match channel 3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 TC Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x8 read-write n 0x0 0x0 RESERVED Reserved. 16 32 TCVAL Timer counter value. 0 16 TCR Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x4 read-write n 0x0 0x0 CEN When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. 0 1 CRESET When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 2 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 2 32 CT16B1 16-bit counter/timers (CT16B0/1) CT16B0 0x0 0x0 0xFFF registers n CT16B1 42 BCCR Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x28 read-write n 0x0 0x0 CAP0FE Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0I Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0RE Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 3 32 BCR0 Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input. 0x2C read-only n 0x0 0x0 CAP Timer counter capture value. 0 16 RESERVED Reserved. 16 32 BCTCR Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x70 read-write n 0x0 0x0 CIS Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. 2 4 ENUM CT16BN_CAP0 CT16Bn_CAP0 0x0 CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). 0 2 ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTHEDGES Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 BEMR External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0]. 0x3C read-write n 0x0 0x0 EM0 External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 0 1 EM1 External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 1 2 EM2 External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 2 3 EM3 External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers. 3 4 EMC0 External Match Control 0. Determines the functionality of External Match 0. 4 6 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. 6 8 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. 8 10 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. 10 12 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 BIR Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. 0x0 read-write n 0x0 0x0 CR0INT Interrupt flag for capture channel 0 event. 4 5 MR0INT Interrupt flag for match channel 0. 0 1 MR1INT Interrupt flag for match channel 1. 1 2 MR2INT Interrupt flag for match channel 2. 2 3 MR3INT Interrupt flag for match channel 3. 3 4 RESERVED Reserved 5 32 BMCR Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x14 read-write n 0x0 0x0 MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0R Reset on MR0: the TC will be reset if MR0 matches it. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 3 4 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1R Reset on MR1: the TC will be reset if MR1 matches it. 4 5 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 5 6 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 6 7 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2R Reset on MR2: the TC will be reset if MR2 matches it. 7 8 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 8 9 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 9 10 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3R Reset on MR3: the TC will be reset if MR3 matches it. 10 11 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 11 12 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 BMR0 Match Register 0 (MR0). MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x30 read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 BMR1 Match Register 0 (MR0). MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x4C read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 BMR2 Match Register 0 (MR0). MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x6C read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 BMR3 Match Register 0 (MR0). MR0 can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x90 read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 BPC Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x10 read-write n 0x0 0x0 PC Prescale counter value. 0 16 RESERVED Reserved. 16 32 BPR Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0xC read-write n 0x0 0x0 PR Prescale max value. 0 16 RESERVED Reserved. 16 32 BPWMC PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0]. 0x74 read-write n 0x0 0x0 PWMEN0 PWM channel0 enable 0 1 ENUM EM0 CT16Bn_MAT0 is controlled by EM0. 0 PWM PWM mode is enabled for CT16Bn_MAT0. 1 PWMEN1 PWM channel1 enable 1 2 ENUM EM1 CT16Bn_MAT1 is controlled by EM1. 0 PWM PWM mode is enabled for CT16Bn_MAT1. 1 PWMEN2 PWM channel2 enable 2 3 ENUM EM2 Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1. 0 PWM PWM mode is enabled for match channel 2 or pin CT16B0_MAT2. 1 PWMEN3 PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out. 3 4 ENUM EM3 Match channel 3 match channel 3 is controlled by EM3. 0 PWM PWM mode is enabled for match channel 3match channel 3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 BTC Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x8 read-write n 0x0 0x0 RESERVED Reserved. 16 32 TC Timer counter value. 0 16 BTCR Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x4 read-write n 0x0 0x0 CEN When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. 0 1 CRESET When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 2 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 2 32 CCR Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x28 read-write n 0x0 0x0 CAP0FE Capture on CT16Bn_CAP0 falling edge: a sequence of 1 then 0 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0I Interrupt on CT16Bn_CAP0 event: a CR0 load due to a CT16Bn_CAP0 event will generate an interrupt. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0RE Capture on CT16Bn_CAP0 rising edge: a sequence of 0 then 1 on CT16Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 3 32 CR0 Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT16B0_CAP0 input. 0x2C read-only n 0x0 0x0 CAP Timer counter capture value. 0 16 RESERVED Reserved. 16 32 CTCR Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x70 read-write n 0x0 0x0 CIS Count Input Select. In counter mode (when bits 1:0 in this register are not 00), these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected in the CTCR register, bits 2:0 in the Capture Control Register (CCR) must be programmed as 000. 2 4 ENUM CT16BN_CAP0 CT16Bn_CAP0 0x0 CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). 0 2 ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTHEDGES Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 EMR External Match Register (EMR). The EMR controls the match function and the external match pins CT16B0_MAT[2:0]. 0x3C read-write n 0x0 0x0 EM0 External Match 0. This bit reflects the state of output CT16B0_MAT0/CT16B1_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT16B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 0 1 EM1 External Match 1. This bit reflects the state of output CT16B0_MAT1/CT16B1_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT16B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 1 2 EM2 External Match 2. This bit reflects the state of output match channel 2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. Note that on counter/timer 0 this match channel is not pinned out. This bit is driven to the CT16B1_MAT2 pin if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 2 3 EM3 External Match 3. This bit reflects the state of output of match channel 3. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. There is no output pin available for this channel on either of the 16-bit timers. 3 4 EMC0 External Match Control 0. Determines the functionality of External Match 0. 4 6 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. 6 8 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. 8 10 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. 10 12 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT16Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT16Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 IR Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. 0x0 read-write n 0x0 0x0 CR0INT Interrupt flag for capture channel 0 event. 4 5 MR0INT Interrupt flag for match channel 0. 0 1 MR1INT Interrupt flag for match channel 1. 1 2 MR2INT Interrupt flag for match channel 2. 2 3 MR3INT Interrupt flag for match channel 3. 3 4 RESERVED Reserved 5 32 MCR Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x14 read-write n 0x0 0x0 MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0R Reset on MR0: the TC will be reset if MR0 matches it. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 3 4 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1R Reset on MR1: the TC will be reset if MR1 matches it. 4 5 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 5 6 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 6 7 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2R Reset on MR2: the TC will be reset if MR2 matches it. 7 8 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 8 9 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 9 10 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3R Reset on MR3: the TC will be reset if MR3 matches it. 10 11 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 11 12 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 MR0 Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x18 -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 MR1 Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x1C -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 MR2 Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x20 -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 MR3 Match Register (MR). MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x24 -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 16 RESERVED Reserved. 16 32 PC Prescale Counter (PC). The 16-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x10 read-write n 0x0 0x0 PCVAL Prescale counter value. 0 16 RESERVED Reserved. 16 32 PR Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0xC read-write n 0x0 0x0 PRVAL Prescale max value. 0 16 RESERVED Reserved. 16 32 PWMC PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT16B0_MAT[2:0]. 0x74 read-write n 0x0 0x0 PWMEN0 PWM channel0 enable 0 1 ENUM EM0 CT16Bn_MAT0 is controlled by EM0. 0 PWM PWM mode is enabled for CT16Bn_MAT0. 1 PWMEN1 PWM channel1 enable 1 2 ENUM EM1 CT16Bn_MAT1 is controlled by EM1. 0 PWM PWM mode is enabled for CT16Bn_MAT1. 1 PWMEN2 PWM channel2 enable 2 3 ENUM EM2 Match channel 2 or pin CT16B0_MAT2 is controlled by EM2. Match channel 2 is not pinned out on timer 1. 0 PWM PWM mode is enabled for match channel 2 or pin CT16B0_MAT2. 1 PWMEN3 PWM channel3 enable Note: It is recommended to use match channel 3 to set the PWM cycle because it is not pinned out. 3 4 ENUM EM3 Match channel 3 match channel 3 is controlled by EM3. 0 PWM PWM mode is enabled for match channel 3match channel 3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 TC Timer Counter (TC). The 16-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x8 read-write n 0x0 0x0 RESERVED Reserved. 16 32 TCVAL Timer counter value. 0 16 TCR Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x4 read-write n 0x0 0x0 CEN When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. 0 1 CRESET When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 2 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 2 32 CT32B0 32-bit counter/timers (CT32B0/1) CT32B0 0x0 0x0 0xFFF registers n CT32B0 43 BCCR Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x28 read-write n 0x0 0x0 CAP0FE Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0I Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0RE Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 3 32 BCR0 Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input. 0x2C read-only n 0x0 0x0 CAP Timer counter capture value. 0 32 BCTCR Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x70 read-write n 0x0 0x0 CIS Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking: 2 4 ENUM CT32BN_CAP0 CT32Bn_CAP0 0x0 CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge 0 2 ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTHEDGES Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 BEMR External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0]. 0x3C read-write n 0x0 0x0 EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 0 1 EM1 External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 1 2 EM2 External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 2 3 EM3 External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 3 4 EMC0 External Match Control 0. Determines the functionality of External Match 0. 4 6 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. 6 8 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. 8 10 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. 10 12 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 BIR Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. 0x0 read-write n 0x0 0x0 CR0INT Interrupt flag for capture channel 0 event. 4 5 MR0INT Interrupt flag for match channel 0. 0 1 MR1INT Interrupt flag for match channel 1. 1 2 MR2INT Interrupt flag for match channel 2. 2 3 MR3INT Interrupt flag for match channel 3. 3 4 RESERVED Reserved 5 32 BMCR Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x14 read-write n 0x0 0x0 MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0R Reset on MR0: the TC will be reset if MR0 matches it. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 3 4 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1R Reset on MR1: the TC will be reset if MR1 matches it. 4 5 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 5 6 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 6 7 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2R Reset on MR2: the TC will be reset if MR2 matches it. 7 8 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 8 9 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 9 10 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3R Reset on MR3: the TC will be reset if MR3 matches it. 10 11 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 11 12 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 BMR0 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x30 read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 BMR1 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x4C read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 BMR2 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x6C read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 BMR3 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x90 read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 BPC Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x10 read-write n 0x0 0x0 PC Prescale counter value. 0 32 BPR Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0xC read-write n 0x0 0x0 PR Prescale value. 0 32 BPWMC PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0]. 0x74 read-write n 0x0 0x0 PWMEN0 PWM channel 0 enable 0 1 ENUM EM0 CT32Bn_MAT0 is controlled by EM0. 0 PWM PWM mode is enabled for CT32Bn_MAT0. 1 PWMEN1 PWM channel 1 enable 1 2 ENUM EM1 CT32Bn_MAT1 is controlled by EM1. 0 PWM PWM mode is enabled for CT32Bn_MAT1. 1 PWMEN2 PWM channel 2 enable 2 3 ENUM EM2 CT32Bn_MAT2 is controlled by EM2. 0 PWM PWM mode is enabled for CT32Bn_MAT2. 1 PWMEN3 PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle. 3 4 ENUM EM3 CT32Bn_MAT3 is controlled by EM3. 0 PWM PWM mode is enabled for CT32Bn_MAT3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 BTC Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x8 read-write n 0x0 0x0 TC Timer counter value. 0 32 BTCR Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x4 read-write n 0x0 0x0 CEN When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. 0 1 CRES When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 2 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 2 32 CCR Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x28 read-write n 0x0 0x0 CAP0FE Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0I Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0RE Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 3 32 CR0 Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input. 0x2C read-only n 0x0 0x0 CAP Timer counter capture value. 0 32 CTCR Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x70 read-write n 0x0 0x0 CIS Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking: 2 4 ENUM CT32BN_CAP0 CT32Bn_CAP0 0x0 CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge 0 2 ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTHEDGES Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 EMR External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0]. 0x3C read-write n 0x0 0x0 EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 0 1 EM1 External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 1 2 EM2 External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 2 3 EM3 External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 3 4 EMC0 External Match Control 0. Determines the functionality of External Match 0. 4 6 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. 6 8 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. 8 10 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. 10 12 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 IR Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. 0x0 read-write n 0x0 0x0 CR0INT Interrupt flag for capture channel 0 event. 4 5 MR0INT Interrupt flag for match channel 0. 0 1 MR1INT Interrupt flag for match channel 1. 1 2 MR2INT Interrupt flag for match channel 2. 2 3 MR3INT Interrupt flag for match channel 3. 3 4 RESERVED Reserved 5 32 MCR Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x14 read-write n 0x0 0x0 MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0R Reset on MR0: the TC will be reset if MR0 matches it. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 3 4 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1R Reset on MR1: the TC will be reset if MR1 matches it. 4 5 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 5 6 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 6 7 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2R Reset on MR2: the TC will be reset if MR2 matches it. 7 8 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 8 9 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 9 10 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3R Reset on MR3: the TC will be reset if MR3 matches it. 10 11 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 11 12 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 MR0 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x18 -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 MR1 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x1C -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 MR2 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x20 -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 MR3 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x24 -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 PC Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x10 read-write n 0x0 0x0 PCVAL Prescale counter value. 0 32 PR Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0xC read-write n 0x0 0x0 PRVAL Prescale value. 0 32 PWMC PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0]. 0x74 read-write n 0x0 0x0 PWMEN0 PWM channel 0 enable 0 1 ENUM EM0 CT32Bn_MAT0 is controlled by EM0. 0 PWM PWM mode is enabled for CT32Bn_MAT0. 1 PWMEN1 PWM channel 1 enable 1 2 ENUM EM1 CT32Bn_MAT1 is controlled by EM1. 0 PWM PWM mode is enabled for CT32Bn_MAT1. 1 PWMEN2 PWM channel 2 enable 2 3 ENUM EM2 CT32Bn_MAT2 is controlled by EM2. 0 PWM PWM mode is enabled for CT32Bn_MAT2. 1 PWMEN3 PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle. 3 4 ENUM EM3 CT32Bn_MAT3 is controlled by EM3. 0 PWM PWM mode is enabled for CT32Bn_MAT3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 TC Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x8 read-write n 0x0 0x0 TCVAL Timer counter value. 0 32 TCR Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x4 read-write n 0x0 0x0 CEN When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. 0 1 CRES When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 2 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 2 32 CT32B1 32-bit counter/timers (CT32B0/1) CT32B0 0x0 0x0 0xFFF registers n CT32B1 44 BCCR Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x28 read-write n 0x0 0x0 CAP0FE Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0I Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0RE Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 3 32 BCR0 Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input. 0x2C read-only n 0x0 0x0 CAP Timer counter capture value. 0 32 BCTCR Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x70 read-write n 0x0 0x0 CIS Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking: 2 4 ENUM CT32BN_CAP0 CT32Bn_CAP0 0x0 CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge 0 2 ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTHEDGES Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 BEMR External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0]. 0x3C read-write n 0x0 0x0 EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 0 1 EM1 External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 1 2 EM2 External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 2 3 EM3 External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 3 4 EMC0 External Match Control 0. Determines the functionality of External Match 0. 4 6 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. 6 8 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. 8 10 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. 10 12 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 BIR Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. 0x0 read-write n 0x0 0x0 CR0INT Interrupt flag for capture channel 0 event. 4 5 MR0INT Interrupt flag for match channel 0. 0 1 MR1INT Interrupt flag for match channel 1. 1 2 MR2INT Interrupt flag for match channel 2. 2 3 MR3INT Interrupt flag for match channel 3. 3 4 RESERVED Reserved 5 32 BMCR Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x14 read-write n 0x0 0x0 MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0R Reset on MR0: the TC will be reset if MR0 matches it. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 3 4 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1R Reset on MR1: the TC will be reset if MR1 matches it. 4 5 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 5 6 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 6 7 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2R Reset on MR2: the TC will be reset if MR2 matches it. 7 8 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 8 9 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 9 10 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3R Reset on MR3: the TC will be reset if MR3 matches it. 10 11 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 11 12 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 BMR0 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x30 read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 BMR1 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x4C read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 BMR2 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x6C read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 BMR3 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR0 matches the TC. 0x90 read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 BPC Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x10 read-write n 0x0 0x0 PC Prescale counter value. 0 32 BPR Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0xC read-write n 0x0 0x0 PR Prescale value. 0 32 BPWMC PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0]. 0x74 read-write n 0x0 0x0 PWMEN0 PWM channel 0 enable 0 1 ENUM EM0 CT32Bn_MAT0 is controlled by EM0. 0 PWM PWM mode is enabled for CT32Bn_MAT0. 1 PWMEN1 PWM channel 1 enable 1 2 ENUM EM1 CT32Bn_MAT1 is controlled by EM1. 0 PWM PWM mode is enabled for CT32Bn_MAT1. 1 PWMEN2 PWM channel 2 enable 2 3 ENUM EM2 CT32Bn_MAT2 is controlled by EM2. 0 PWM PWM mode is enabled for CT32Bn_MAT2. 1 PWMEN3 PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle. 3 4 ENUM EM3 CT32Bn_MAT3 is controlled by EM3. 0 PWM PWM mode is enabled for CT32Bn_MAT3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 BTC Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x8 read-write n 0x0 0x0 TC Timer counter value. 0 32 BTCR Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x4 read-write n 0x0 0x0 CEN When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. 0 1 CRES When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 2 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 2 32 CCR Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. 0x28 read-write n 0x0 0x0 CAP0FE Capture on CT32Bn_CAP0 falling edge: a sequence of 1 then 0 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0I Interrupt on CT32Bn_CAP0 event: a CR0 load due to a CT32Bn_CAP0 event will generate an interrupt. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CAP0RE Capture on CT32Bn_CAP0 rising edge: a sequence of 0 then 1 on CT32Bn_CAP0 will cause CR0 to be loaded with the contents of TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 3 32 CR0 Capture Register 0 (CR0). CR0 is loaded with the value of TC when there is an event on the CT32B0_CAP0 input. 0x2C read-only n 0x0 0x0 CAP Timer counter capture value. 0 32 CTCR Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. 0x70 read-write n 0x0 0x0 CIS Count Input Select. When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking: 2 4 ENUM CT32BN_CAP0 CT32Bn_CAP0 0x0 CTM Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: every rising PCLK edge 0 2 ENUM TIMER_MODE_EVERY_RI Timer Mode: every rising PCLK edge 0x0 RISING Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2. 0x1 FALLLING Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2. 0x2 BOTHEDGES Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 EMR External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0]. 0x3C read-write n 0x0 0x0 EM0 External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 0 1 EM1 External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 1 2 EM2 External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 2 3 EM3 External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH). 3 4 EMC0 External Match Control 0. Determines the functionality of External Match 0. 4 6 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC1 External Match Control 1. Determines the functionality of External Match 1. 6 8 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC2 External Match Control 2. Determines the functionality of External Match 2. 8 10 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 EMC3 External Match Control 3. Determines the functionality of External Match 3. 10 12 ENUM DO_NOTHING_ Do Nothing. 0x0 CLEAR_THE_CORRESPOND Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out). 0x1 SET_THE_CORRESPONDIN Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out). 0x2 TOGGLE_THE_CORRESPON Toggle the corresponding External Match bit/output. 0x3 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 IR Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending. 0x0 read-write n 0x0 0x0 CR0INT Interrupt flag for capture channel 0 event. 4 5 MR0INT Interrupt flag for match channel 0. 0 1 MR1INT Interrupt flag for match channel 1. 1 2 MR2INT Interrupt flag for match channel 2. 2 3 MR3INT Interrupt flag for match channel 3. 3 4 RESERVED Reserved 5 32 MCR Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. 0x14 read-write n 0x0 0x0 MR0I Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 1 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0R Reset on MR0: the TC will be reset if MR0 matches it. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR0S Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1I Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 3 4 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1R Reset on MR1: the TC will be reset if MR1 matches it. 4 5 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 5 6 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2I Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 6 7 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2R Reset on MR2: the TC will be reset if MR2 matches it. 7 8 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR2S Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 8 9 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3I Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 9 10 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3R Reset on MR3: the TC will be reset if MR3 matches it. 10 11 ENUM DISABLED Disabled 0 ENABLED Enabled 1 MR3S Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 11 12 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 12 32 MR0 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x18 -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 MR1 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x1C -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 MR2 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x20 -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 MR3 Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. 0x24 -1 read-write n 0x0 0x0 MATCH Timer counter match value. 0 32 PC Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. 0x10 read-write n 0x0 0x0 PCVAL Prescale counter value. 0 32 PR Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC. 0xC read-write n 0x0 0x0 PRVAL Prescale value. 0 32 PWMC PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0]. 0x74 read-write n 0x0 0x0 PWMEN0 PWM channel 0 enable 0 1 ENUM EM0 CT32Bn_MAT0 is controlled by EM0. 0 PWM PWM mode is enabled for CT32Bn_MAT0. 1 PWMEN1 PWM channel 1 enable 1 2 ENUM EM1 CT32Bn_MAT1 is controlled by EM1. 0 PWM PWM mode is enabled for CT32Bn_MAT1. 1 PWMEN2 PWM channel 2 enable 2 3 ENUM EM2 CT32Bn_MAT2 is controlled by EM2. 0 PWM PWM mode is enabled for CT32Bn_MAT2. 1 PWMEN3 PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle. 3 4 ENUM EM3 CT32Bn_MAT3 is controlled by EM3. 0 PWM PWM mode is enabled for CT32Bn_MAT3. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 TC Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR. 0x8 read-write n 0x0 0x0 TCVAL Timer counter value. 0 32 TCR Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. 0x4 read-write n 0x0 0x0 CEN When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled. 0 1 CRES When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero. 1 2 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 2 32 FMC Flash memory programming firmware FMC 0x0 0x0 0xFFF registers n FLASHCFG Flash configuration register 0x10 read-write n 0x0 0x0 FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access. 0 2 ENUM 1_SYSTEM_CLOCK_FLASH 1 system clock flash access time (for system clock frequencies of up to 20 MHz). 0x0 2_SYSTEM_CLOCKS_FLAS 2 system clocks flash access time (for system clock frequencies of up to 40 MHz). 0x1 3_SYSTEM_CLOCKS_FLAS 3 system clocks flash access time (for system clock frequencies of up to 72 MHz). 0x2 RESERVED_ Reserved. 0x3 RESERVED Reserved. User software must not change the value of these bits. Bits 31:2 must be written back exactly as read. 2 32 FMSSTART Signature start address register 0x20 read-write n 0x0 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 17 32 START Signature generation start address (corresponds to AHB byte address bits[20:4]). 0 17 FMSSTOP Signature stop-address register 0x24 read-write n 0x0 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 18 32 SIG_START Start control bit for signature generation. 17 18 ENUM SIGNATURE_GENERATION Signature generation is stopped 0 INITIATE_SIGNATURE_G Initiate signature generation 1 STOP BIST stop address divided by 16 (corresponds to AHB byte address [20:4]). 0 17 FMSTAT Signature generation status register 0xFE0 read-only n 0x0 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 3 32 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 3 32 SIG_DONE When 1, a previously started signature generation has completed. See FMSTATCLR register description for clearing this flag. 2 3 FMSTATCLR Signature generation status clear register 0xFE8 write-only n 0x0 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 3 32 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 3 32 SIG_DONE_CLR Writing a 1 to this bits clears the signature generation completion flag (SIG_DONE) in the FMSTAT register. 2 3 FMSW0 Word 0 [31:0] 0x2C read-only n 0x0 0x0 SW0_31_0 Word 0 of 128-bit signature (bits 31 to 0). 0 32 FMSW1 Word 1 [63:32] 0x30 read-only n 0x0 0x0 SW1_63_32 Word 1 of 128-bit signature (bits 63 to 32). 0 32 FMSW2 Word 2 [95:64] 0x34 read-only n 0x0 0x0 SW2_95_64 Word 2 of 128-bit signature (bits 95 to 64). 0 32 FMSW3 Word 3 [127:96] 0x38 read-only n 0x0 0x0 SW3_127_96 Word 3 of 128-bit signature (bits 127 to 96). 0 32 GPIO0 General Purpose I/O (GPIO) GPIO 0x0 0x0 0xFFFFF registers n PIO_0 56 DATA Port n data register for pins PIOn_0 to PIOn_11 0x3FFC read-write n 0x0 0x0 DATA0 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 0 1 DATA1 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 1 2 DATA10 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 10 11 DATA11 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 11 12 DATA2 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 2 3 DATA3 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 3 4 DATA4 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 4 5 DATA5 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 5 6 DATA6 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 6 7 DATA7 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 7 8 DATA8 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 8 9 DATA9 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 9 10 RESERVED Reserved 12 32 DIR Data direction register for port n 0x8000 read-write n 0x0 0x0 IO0 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 0 1 IO1 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 1 2 IO10 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 10 11 IO11 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 11 12 IO2 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 2 3 IO3 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 3 4 IO4 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 4 5 IO5 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 5 6 IO6 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 6 7 IO7 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 7 8 IO8 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 8 9 IO9 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 9 10 RESERVED Reserved 12 32 IBE Interrupt both edges register for port n 0x8008 read-write n 0x0 0x0 IBE0 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 0 1 IBE1 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 1 2 IBE10 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 10 11 IBE11 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 11 12 IBE2 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 2 3 IBE3 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 3 4 IBE4 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 4 5 IBE5 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 5 6 IBE6 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 6 7 IBE7 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 7 8 IBE8 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 8 9 IBE9 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 9 10 RESERVED Reserved 12 32 IC Interrupt clear register for port n 0x801C write-only n 0x0 0x0 CLR0 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 0 1 CLR1 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 1 2 CLR10 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 10 11 CLR11 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 11 12 CLR2 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 2 3 CLR3 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 3 4 CLR4 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 4 5 CLR5 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 5 6 CLR6 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 6 7 CLR7 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 7 8 CLR8 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 8 9 CLR9 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 9 10 RESERVED Reserved 12 32 IE Interrupt mask register for port n 0x8010 read-write n 0x0 0x0 MASK0 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 0 1 MASK1 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 1 2 MASK10 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 10 11 MASK11 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 11 12 MASK2 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 2 3 MASK3 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 3 4 MASK4 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 4 5 MASK5 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 5 6 MASK6 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 6 7 MASK7 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 7 8 MASK8 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 8 9 MASK9 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 9 10 RESERVED Reserved 12 32 IEV Interrupt event register for port n 0x800C read-write n 0x0 0x0 IEV0 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 0 1 IEV1 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 1 2 IEV10 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 10 11 IEV11 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 11 12 IEV2 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 2 3 IEV3 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 3 4 IEV4 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 4 5 IEV5 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 5 6 IEV6 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 6 7 IEV7 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 7 8 IEV8 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 8 9 IEV9 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 9 10 RESERVED Reserved 12 32 IS Interrupt sense register for port n 0x8004 read-write n 0x0 0x0 ISENSE0 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 0 1 ISENSE1 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 1 2 ISENSE10 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 10 11 ISENSE11 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 11 12 ISENSE2 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 2 3 ISENSE3 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 3 4 ISENSE4 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 4 5 ISENSE5 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 5 6 ISENSE6 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 6 7 ISENSE7 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 7 8 ISENSE8 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 8 9 ISENSE9 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 9 10 RESERVED Reserved 12 32 MIS Masked interrupt status register for port n 0x8018 read-only n 0x0 0x0 MASK0 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 0 1 MASK1 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 1 2 MASK10 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 10 11 MASK11 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 11 12 MASK2 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 2 3 MASK3 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 3 4 MASK4 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 4 5 MASK5 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 5 6 MASK6 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 6 7 MASK7 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 7 8 MASK8 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 8 9 MASK9 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 9 10 RESERVED Reserved 12 32 RIS Raw interrupt status register for port n 0x8014 read-only n 0x0 0x0 RAWST0 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 0 1 RAWST1 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 1 2 RAWST10 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 10 11 RAWST11 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 11 12 RAWST2 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 2 3 RAWST3 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 3 4 RAWST4 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 4 5 RAWST5 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 5 6 RAWST6 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 6 7 RAWST7 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 7 8 RAWST8 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 8 9 RAWST9 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 9 10 RESERVED Reserved 12 32 GPIO1 General Purpose I/O (GPIO) GPIO 0x0 0x0 0xFFFFF registers n PIO_1 55 DATA Port n data register for pins PIOn_0 to PIOn_11 0x3FFC read-write n 0x0 0x0 DATA0 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 0 1 DATA1 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 1 2 DATA10 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 10 11 DATA11 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 11 12 DATA2 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 2 3 DATA3 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 3 4 DATA4 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 4 5 DATA5 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 5 6 DATA6 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 6 7 DATA7 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 7 8 DATA8 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 8 9 DATA9 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 9 10 RESERVED Reserved 12 32 DIR Data direction register for port n 0x8000 read-write n 0x0 0x0 IO0 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 0 1 IO1 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 1 2 IO10 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 10 11 IO11 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 11 12 IO2 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 2 3 IO3 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 3 4 IO4 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 4 5 IO5 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 5 6 IO6 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 6 7 IO7 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 7 8 IO8 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 8 9 IO9 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 9 10 RESERVED Reserved 12 32 IBE Interrupt both edges register for port n 0x8008 read-write n 0x0 0x0 IBE0 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 0 1 IBE1 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 1 2 IBE10 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 10 11 IBE11 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 11 12 IBE2 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 2 3 IBE3 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 3 4 IBE4 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 4 5 IBE5 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 5 6 IBE6 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 6 7 IBE7 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 7 8 IBE8 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 8 9 IBE9 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 9 10 RESERVED Reserved 12 32 IC Interrupt clear register for port n 0x801C write-only n 0x0 0x0 CLR0 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 0 1 CLR1 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 1 2 CLR10 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 10 11 CLR11 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 11 12 CLR2 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 2 3 CLR3 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 3 4 CLR4 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 4 5 CLR5 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 5 6 CLR6 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 6 7 CLR7 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 7 8 CLR8 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 8 9 CLR9 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 9 10 RESERVED Reserved 12 32 IE Interrupt mask register for port n 0x8010 read-write n 0x0 0x0 MASK0 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 0 1 MASK1 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 1 2 MASK10 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 10 11 MASK11 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 11 12 MASK2 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 2 3 MASK3 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 3 4 MASK4 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 4 5 MASK5 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 5 6 MASK6 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 6 7 MASK7 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 7 8 MASK8 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 8 9 MASK9 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 9 10 RESERVED Reserved 12 32 IEV Interrupt event register for port n 0x800C read-write n 0x0 0x0 IEV0 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 0 1 IEV1 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 1 2 IEV10 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 10 11 IEV11 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 11 12 IEV2 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 2 3 IEV3 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 3 4 IEV4 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 4 5 IEV5 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 5 6 IEV6 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 6 7 IEV7 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 7 8 IEV8 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 8 9 IEV9 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 9 10 RESERVED Reserved 12 32 IS Interrupt sense register for port n 0x8004 read-write n 0x0 0x0 ISENSE0 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 0 1 ISENSE1 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 1 2 ISENSE10 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 10 11 ISENSE11 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 11 12 ISENSE2 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 2 3 ISENSE3 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 3 4 ISENSE4 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 4 5 ISENSE5 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 5 6 ISENSE6 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 6 7 ISENSE7 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 7 8 ISENSE8 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 8 9 ISENSE9 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 9 10 RESERVED Reserved 12 32 MIS Masked interrupt status register for port n 0x8018 read-only n 0x0 0x0 MASK0 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 0 1 MASK1 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 1 2 MASK10 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 10 11 MASK11 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 11 12 MASK2 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 2 3 MASK3 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 3 4 MASK4 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 4 5 MASK5 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 5 6 MASK6 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 6 7 MASK7 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 7 8 MASK8 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 8 9 MASK9 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 9 10 RESERVED Reserved 12 32 RIS Raw interrupt status register for port n 0x8014 read-only n 0x0 0x0 RAWST0 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 0 1 RAWST1 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 1 2 RAWST10 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 10 11 RAWST11 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 11 12 RAWST2 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 2 3 RAWST3 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 3 4 RAWST4 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 4 5 RAWST5 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 5 6 RAWST6 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 6 7 RAWST7 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 7 8 RAWST8 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 8 9 RAWST9 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 9 10 RESERVED Reserved 12 32 GPIO2 General Purpose I/O (GPIO) GPIO 0x0 0x0 0xFFFFF registers n PIO_2 54 DATA Port n data register for pins PIOn_0 to PIOn_11 0x3FFC read-write n 0x0 0x0 DATA0 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 0 1 DATA1 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 1 2 DATA10 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 10 11 DATA11 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 11 12 DATA2 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 2 3 DATA3 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 3 4 DATA4 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 4 5 DATA5 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 5 6 DATA6 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 6 7 DATA7 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 7 8 DATA8 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 8 9 DATA9 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 9 10 RESERVED Reserved 12 32 DIR Data direction register for port n 0x8000 read-write n 0x0 0x0 IO0 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 0 1 IO1 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 1 2 IO10 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 10 11 IO11 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 11 12 IO2 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 2 3 IO3 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 3 4 IO4 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 4 5 IO5 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 5 6 IO6 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 6 7 IO7 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 7 8 IO8 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 8 9 IO9 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 9 10 RESERVED Reserved 12 32 IBE Interrupt both edges register for port n 0x8008 read-write n 0x0 0x0 IBE0 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 0 1 IBE1 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 1 2 IBE10 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 10 11 IBE11 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 11 12 IBE2 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 2 3 IBE3 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 3 4 IBE4 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 4 5 IBE5 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 5 6 IBE6 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 6 7 IBE7 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 7 8 IBE8 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 8 9 IBE9 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 9 10 RESERVED Reserved 12 32 IC Interrupt clear register for port n 0x801C write-only n 0x0 0x0 CLR0 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 0 1 CLR1 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 1 2 CLR10 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 10 11 CLR11 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 11 12 CLR2 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 2 3 CLR3 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 3 4 CLR4 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 4 5 CLR5 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 5 6 CLR6 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 6 7 CLR7 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 7 8 CLR8 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 8 9 CLR9 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 9 10 RESERVED Reserved 12 32 IE Interrupt mask register for port n 0x8010 read-write n 0x0 0x0 MASK0 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 0 1 MASK1 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 1 2 MASK10 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 10 11 MASK11 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 11 12 MASK2 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 2 3 MASK3 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 3 4 MASK4 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 4 5 MASK5 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 5 6 MASK6 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 6 7 MASK7 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 7 8 MASK8 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 8 9 MASK9 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 9 10 RESERVED Reserved 12 32 IEV Interrupt event register for port n 0x800C read-write n 0x0 0x0 IEV0 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 0 1 IEV1 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 1 2 IEV10 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 10 11 IEV11 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 11 12 IEV2 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 2 3 IEV3 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 3 4 IEV4 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 4 5 IEV5 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 5 6 IEV6 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 6 7 IEV7 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 7 8 IEV8 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 8 9 IEV9 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 9 10 RESERVED Reserved 12 32 IS Interrupt sense register for port n 0x8004 read-write n 0x0 0x0 ISENSE0 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 0 1 ISENSE1 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 1 2 ISENSE10 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 10 11 ISENSE11 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 11 12 ISENSE2 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 2 3 ISENSE3 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 3 4 ISENSE4 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 4 5 ISENSE5 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 5 6 ISENSE6 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 6 7 ISENSE7 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 7 8 ISENSE8 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 8 9 ISENSE9 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 9 10 RESERVED Reserved 12 32 MIS Masked interrupt status register for port n 0x8018 read-only n 0x0 0x0 MASK0 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 0 1 MASK1 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 1 2 MASK10 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 10 11 MASK11 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 11 12 MASK2 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 2 3 MASK3 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 3 4 MASK4 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 4 5 MASK5 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 5 6 MASK6 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 6 7 MASK7 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 7 8 MASK8 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 8 9 MASK9 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 9 10 RESERVED Reserved 12 32 RIS Raw interrupt status register for port n 0x8014 read-only n 0x0 0x0 RAWST0 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 0 1 RAWST1 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 1 2 RAWST10 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 10 11 RAWST11 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 11 12 RAWST2 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 2 3 RAWST3 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 3 4 RAWST4 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 4 5 RAWST5 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 5 6 RAWST6 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 6 7 RAWST7 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 7 8 RAWST8 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 8 9 RAWST9 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 9 10 RESERVED Reserved 12 32 GPIO3 General Purpose I/O (GPIO) GPIO 0x0 0x0 0xFFFFF registers n PIO_3 53 DATA Port n data register for pins PIOn_0 to PIOn_11 0x3FFC read-write n 0x0 0x0 DATA0 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 0 1 DATA1 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 1 2 DATA10 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 10 11 DATA11 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 11 12 DATA2 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 2 3 DATA3 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 3 4 DATA4 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 4 5 DATA5 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 5 6 DATA6 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 6 7 DATA7 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 7 8 DATA8 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 8 9 DATA9 Logic levels for pins PIOn_0 to PIOn_11. HIGH = 1, LOW = 0. 9 10 RESERVED Reserved 12 32 DIR Data direction register for port n 0x8000 read-write n 0x0 0x0 IO0 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 0 1 IO1 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 1 2 IO10 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 10 11 IO11 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 11 12 IO2 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 2 3 IO3 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 3 4 IO4 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 4 5 IO5 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 5 6 IO6 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 6 7 IO7 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 7 8 IO8 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 8 9 IO9 Selects pin x as input or output (x = 0 to 11). 0 = Pin PIOn_x is configured as input. 1 = Pin PIOn_x is configured as output. 9 10 RESERVED Reserved 12 32 IBE Interrupt both edges register for port n 0x8008 read-write n 0x0 0x0 IBE0 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 0 1 IBE1 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 1 2 IBE10 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 10 11 IBE11 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 11 12 IBE2 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 2 3 IBE3 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 3 4 IBE4 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 4 5 IBE5 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 5 6 IBE6 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 6 7 IBE7 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 7 8 IBE8 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 8 9 IBE9 Selects interrupt on pin x to be triggered on both edges (x = 0 to 11). 0 = Interrupt on pin PIOn_x is controlled through register GPIOIEV. 1 = Both edges on pin PIOn_x trigger an interrupt. 9 10 RESERVED Reserved 12 32 IC Interrupt clear register for port n 0x801C write-only n 0x0 0x0 CLR0 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 0 1 CLR1 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 1 2 CLR10 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 10 11 CLR11 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 11 12 CLR2 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 2 3 CLR3 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 3 4 CLR4 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 4 5 CLR5 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 5 6 CLR6 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 6 7 CLR7 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 7 8 CLR8 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 8 9 CLR9 Selects interrupt on pin x to be cleared (x = 0 to 11). Clears the interrupt edge detection logic. This register is write-only. The synchronizer between the GPIO and the NVIC blocks causes a delay of 2 clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection logic before the exit of the interrupt service routine. 0 = No effect. 1 = Clears edge detection logic for pin PIOn_x. 9 10 RESERVED Reserved 12 32 IE Interrupt mask register for port n 0x8010 read-write n 0x0 0x0 MASK0 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 0 1 MASK1 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 1 2 MASK10 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 10 11 MASK11 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 11 12 MASK2 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 2 3 MASK3 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 3 4 MASK4 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 4 5 MASK5 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 5 6 MASK6 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 6 7 MASK7 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 7 8 MASK8 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 8 9 MASK9 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = Interrupt on pin PIOn_x is masked. 1 = Interrupt on pin PIOn_x is not masked. 9 10 RESERVED Reserved 12 32 IEV Interrupt event register for port n 0x800C read-write n 0x0 0x0 IEV0 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 0 1 IEV1 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 1 2 IEV10 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 10 11 IEV11 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 11 12 IEV2 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 2 3 IEV3 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 3 4 IEV4 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 4 5 IEV5 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 5 6 IEV6 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 6 7 IEV7 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 7 8 IEV8 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 8 9 IEV9 Selects interrupt on pin x to be triggered rising or falling edges (x = 0 to 11). 0 = Depending on setting in register GPIOIS (see Table 151), falling edges or LOW level on pin PIOn_x trigger an interrupt. 1 = Depending on setting in register GPIOIS (see Table 151), rising edges or HIGH level on pin PIOn_x trigger an interrupt. 9 10 RESERVED Reserved 12 32 IS Interrupt sense register for port n 0x8004 read-write n 0x0 0x0 ISENSE0 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 0 1 ISENSE1 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 1 2 ISENSE10 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 10 11 ISENSE11 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 11 12 ISENSE2 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 2 3 ISENSE3 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 3 4 ISENSE4 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 4 5 ISENSE5 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 5 6 ISENSE6 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 6 7 ISENSE7 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 7 8 ISENSE8 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 8 9 ISENSE9 Selects interrupt on pin x as level or edge sensitive (x = 0 to 11). 0 = Interrupt on pin PIOn_x is configured as edge sensitive. 1 = Interrupt on pin PIOn_x is configured as level sensitive. 9 10 RESERVED Reserved 12 32 MIS Masked interrupt status register for port n 0x8018 read-only n 0x0 0x0 MASK0 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 0 1 MASK1 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 1 2 MASK10 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 10 11 MASK11 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 11 12 MASK2 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 2 3 MASK3 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 3 4 MASK4 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 4 5 MASK5 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 5 6 MASK6 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 6 7 MASK7 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 7 8 MASK8 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 8 9 MASK9 Selects interrupt on pin x to be masked (x = 0 to 11). 0 = No interrupt or interrupt masked on pin PIOn_x. 1 = Interrupt on PIOn_x. 9 10 RESERVED Reserved 12 32 RIS Raw interrupt status register for port n 0x8014 read-only n 0x0 0x0 RAWST0 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 0 1 RAWST1 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 1 2 RAWST10 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 10 11 RAWST11 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 11 12 RAWST2 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 2 3 RAWST3 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 3 4 RAWST4 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 4 5 RAWST5 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 5 6 RAWST6 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 6 7 RAWST7 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 7 8 RAWST8 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 8 9 RAWST9 Raw interrupt status (x = 0 to 11). 0 = No interrupt on pin PIOn_x. 1 = Interrupt requirements met on PIOn_x. 9 10 RESERVED Reserved 12 32 I2C I2C-bus controller I2C 0x0 0x0 0xFFF registers n I2C0 40 ADR0 I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0xC read-write n 0x0 0x0 Address The I2C device address for slave mode. 1 8 GC General Call enable bit. 0 1 RESERVED Reserved. The value read from a reserved bit is not defined. 8 32 ADR1 I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0x20 -1 read-write n 0x0 0x0 Address The I2C device address for slave mode. 1 8 GC General Call enable bit. 0 1 RESERVED Reserved. The value read from a reserved bit is not defined. 8 32 ADR2 I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0x24 -1 read-write n 0x0 0x0 Address The I2C device address for slave mode. 1 8 GC General Call enable bit. 0 1 RESERVED Reserved. The value read from a reserved bit is not defined. 8 32 ADR3 I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address. 0x28 -1 read-write n 0x0 0x0 Address The I2C device address for slave mode. 1 8 GC General Call enable bit. 0 1 RESERVED Reserved. The value read from a reserved bit is not defined. 8 32 CONCLR I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register. 0x18 write-only n 0x0 0x0 AAC Assert acknowledge Clear bit. 2 3 I2ENC I2C interface Disable bit. 6 7 RESERVED Reserved. The value read from a reserved bit is not defined. 8 32 RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 5 RESERVED Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined. 7 8 RESERVED Reserved. The value read from a reserved bit is not defined. 8 32 SIC I2C interrupt Clear bit. 3 4 STAC START flag Clear bit. 5 6 CONSET I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register. 0x0 read-write n 0x0 0x0 AA Assert acknowledge flag. 2 3 I2EN I2C interface enable. 6 7 RESERVED Reserved. The value read from a reserved bit is not defined. 7 32 RESERVED Reserved. The value read from a reserved bit is not defined. 7 32 SI I2C interrupt flag. 3 4 STA START flag. 5 6 STO STOP flag. 4 5 DAT I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register. 0x8 read-write n 0x0 0x0 Data This register holds data values that have been received or are to be transmitted. 0 8 RESERVED Reserved. The value read from a reserved bit is not defined. 8 32 DATA_BUFFER Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus. 0x2C read-only n 0x0 0x0 Data This register holds contents of the 8 MSBs of the I2DAT shift register. 0 8 RESERVED Reserved. The value read from a reserved bit is not defined. 8 32 MASK0 I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). 0x30 -1 read-write n 0x0 0x0 MASK Mask bits. 1 8 RESERVED Reserved. The value read from reserved bits is undefined. 8 32 RESERVED Reserved. The value read from reserved bits is undefined. 8 32 MASK1 I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). 0x34 -1 read-write n 0x0 0x0 MASK Mask bits. 1 8 RESERVED Reserved. The value read from reserved bits is undefined. 8 32 RESERVED Reserved. The value read from reserved bits is undefined. 8 32 MASK2 I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). 0x38 -1 read-write n 0x0 0x0 MASK Mask bits. 1 8 RESERVED Reserved. The value read from reserved bits is undefined. 8 32 RESERVED Reserved. The value read from reserved bits is undefined. 8 32 MASK3 I2C Slave address mask register n. This mask register is associated with I2ADRn to determine an address match. The mask register has no effect when comparing to the General Call address (0000000). 0x3C -1 read-write n 0x0 0x0 MASK Mask bits. 1 8 RESERVED Reserved. The value read from reserved bits is undefined. 8 32 RESERVED Reserved. The value read from reserved bits is undefined. 8 32 MMCTRL Monitor mode control register. 0x1C read-write n 0x0 0x0 ENA_SCL SCL output enable. 1 2 ENUM HIGH When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line. 0 NORMAL When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1] 1 MATCH_ALL Select interrupt register match. 2 3 ENUM MATCH When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned. 0 ANYINT When this bit is set to 1 and the I 2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus. 1 MM_ENA Monitor mode enable. 0 1 ENUM DISABLED Monitor mode disabled. 0 ENABLED The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line. 1 RESERVED Reserved. The value read from reserved bits is not defined. 3 32 SCLH SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock. 0x10 read-write n 0x0 0x0 RESERVED Reserved. The value read from a reserved bit is not defined. 16 32 SCLH Count for SCL HIGH time period selection. 0 16 SCLL SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode. 0x14 read-write n 0x0 0x0 RESERVED Reserved. The value read from a reserved bit is not defined. 16 32 SCLL Count for SCL low time period selection. 0 16 STAT I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed. 0x4 read-only n 0x0 0x0 RESERVED Reserved. The value read from a reserved bit is not defined. 8 32 RESERVED Reserved. The value read from a reserved bit is not defined. 8 32 Status These bits give the actual status information about the I 2C interface. 3 8 IOCON I/O configuration IOCON 0x0 0x0 0xFFF registers n DCD_LOC DCD pin location select register 0xB8 read-write n 0x0 0x0 DCDLOC Selects pin location for DCD pin (this register is only used for parts LPC1311/01 and LPC1313/01). 0 2 ENUM SELECTS_DCD_FUNCTION Selects DCD function in pin location PIO2_2/DCD/MISO1. 0x0 SELECTS_DCD_FUNCTIO Selects DCD function in pin location PIO3_2/DCD. 0x1 RESERVED_ Reserved. 0x3 RESERVED_ Reserved. 0x3 RESERVED Reserved. 2 32 DSR_LOC DSR pin location select register 0xB4 read-write n 0x0 0x0 DSRLOC Selects pin location for DSR0 pin (this register is only used for parts LPC1311/01 and LPC1313/01). 0 2 ENUM SELECTS_DSR_FUNCTION Selects DSR function in pin location PIO3_1/DSR. 0x1 SELECTS_DSR_FUNCTION Selects DSR function in pin location PIO3_1/DSR. 0x1 RESERVED_ Reserved. 0x3 RESERVED_ Reserved. 0x3 RESERVED Reserved. 2 32 PIO0_1 I/O configuration for pin PIO0_1/CLKOUT/ CT32B0_MAT2/USB_FTOGGLE 0x10 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO0_1. 0x0 CLK Selects function CLKOUT. 0x1 CT3 Selects function CT32B0_MAT2. 0x2 USB Selects function USB_FTOGGLE (function not available on all parts) 0x3 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO0_2 I/O configuration for pin PIO0_2/SSEL0/ CT16B0_CAP0 0x1C read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO0_2. 0x0 SSE Selects function SSEL0. 0x1 CT1 Selects function CT16B0_CAP0. 0x2 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO0_3 I/O configuration for pin PIO0_3/USB_VBUS 0x2C read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO0_3. 0x0 USB Selects function USB_VBUS (function not available on all parts). 0x1 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO0_4 I/O configuration for pin PIO0_4/SCL 0x30 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO0_4 (open-drain pin). 0x0 SELECTS_I2C_FUNCTION Selects I2C function SCL (open-drain pin). 0x1 I2CMODE Selects I2C mode. Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). 8 10 ENUM STANDARD_MODE/_FAST_ Standard mode/ Fast-mode I2C 0x0 STANDARDFAST_ Standard mode/ Fast-mode I2C 0x0 STANDARD_I/O_FUNCTIO Standard I/O functionality 0x1 STANDARDIO Standard I/O functionality 0x1 FAST_MODE_PLUS_I2C Fast-mode Plus I2C 0x2 RESERVED Reserved 0x3 RESERVED Reserved 10 32 RESERVED Reserved 10 32 PIO0_5 I/O configuration for pin PIO0_5/SDA 0x34 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO0_5 (open-drain pin). 0x0 SELECTS_I2C_FUNCTION Selects I2C function SDA (open-drain pin). 0x1 I2CMODE Selects I2C mode. Select Standard mode (I2CMODE = 00, default) or Standard I/O functionality (I2CMODE = 01) if the pin function is GPIO (FUNC = 000). 8 10 ENUM STANDARD_MODE/_FAST_ Standard mode/ Fast-mode I2C 0x0 STANDARDFAST Standard mode/ Fast-mode I2C 0x0 STANDARD_I/O_FUNCTIO Standard I/O functionality 0x1 STANDARDIO Standard I/O functionality 0x1 FAST_MODE_PLUS_I2C Fast-mode Plus I2C 0x2 RESERVED Reserved 0x3 RESERVED Reserved 10 32 RESERVED Reserved 10 32 PIO0_6 I/O configuration for pin PIO0_6/USB_CONNECT/SCK 0x4C read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO0_6. 0x0 USB Selects function USB_CONNECT (function not available on all parts). 0x1 SCK Selects function SCK0 (only if pin PIO0_6/ USB_CONNECT/ SCK0 selected in Table 139). 0x2 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO0_7 I/O configuration for pin PIO0_7/CTS 0x50 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO0_7. 0x0 CTS_ Select function CTS. 0x1 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO0_8 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 0x60 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO0_8. 0x0 MIS Selects function MISO0. 0x1 CT1 Selects function CT16B0_MAT0. 0x2 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO0_9 I/O configuration for pin PIO0_9/MOSI0/ CT16B0_MAT1/SWO 0x64 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO0_9. 0x0 MOS Selects function MOSI0. 0x1 CT1 Selects function CT16B0_MAT1. 0x2 SWO Selects function SWO 0x3 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO1_10 I/O configuration for pin PIO1_10/AD6/ CT16B1_MAT1 0x6C read-write n 0x0 0x0 ADMODE Selects Analog/Digital mode 7 8 ENUM ANALOG_INPUT_MODE Analog input mode 0 DIGITAL_FUNCTIONAL_M Digital functional mode 1 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO1_10. 0x0 AD6 Selects function AD6. 0x1 CT1 Selects function CT16B1_MAT1. 0x2 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 8 10 RESERVED Reserved 11 32 PIO1_11 I/O configuration for pin PIO1_11/AD7 0x98 read-write n 0x0 0x0 ADMODE Selects Analog/Digital mode 7 8 ENUM ANALOG_INPUT_MODE Analog input mode 0 DIGITAL_FUNCTIONAL_M Digital functional mode 1 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO1_11. 0x0 AD7 Selects function AD7. 0x1 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 8 10 RESERVED Reserved 11 32 PIO1_4 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 0x94 read-write n 0x0 0x0 ADMODE Selects Analog/Digital mode 7 8 ENUM ANALOG_INPUT_MODE Analog input mode 0 DIGITAL_FUNCTIONAL_M Digital functional mode 1 FUNC Selects pin function. This pin functions as WAKEUP pin if the LPC13xx is in Deep power-down mode regardless of the value of FUNC. All other values are reserved. 0 3 ENUM PIO Selects function PIO1_4. 0x0 AD5 Selects function AD5. 0x1 CT3 Selects function CT32B1_MAT3. 0x2 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 8 10 RESERVED Reserved 11 32 PIO1_5 I/O configuration for pin PIO1_5/RTS/CT32B0_CAP0 0xA0 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO1_5. 0x0 RTS Selects function RTS. 0x1 CT3 Selects function CT32B0_CAP0. 0x2 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO1_6 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 0xA4 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO1_6. 0x0 RXD Selects function RXD. 0x1 CT3 Selects function CT32B0_MAT0. 0x2 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO1_7 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 0xA8 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO1_7. 0x0 TXD Selects function TXD. 0x1 CT3 Selects function CT32B0_MAT1. 0x2 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO1_8 I/O configuration for pin PIO1_8/CT16B1_CAP0 0x14 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO1_8. 0x0 CT1 Selects function CT16B1_CAP0. 0x1 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO1_9 I/O configuration for pin PIO1_9/CT16B1_MAT0 0x38 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO1_9. 0x0 CT1 Selects function CT16B1_MAT0. 0x1 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO2_0 I/O configuration for pin PIO2_0/DTR/SSEL1 0x8 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO2 Select function PIO2_0. 0x0 DTR_ Select function DTR. 0x1 SSEL Select function SSEL1 (function not available on all parts). 0x2 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO2_1 I/O configuration for pin PIO2_1/DSR/SCK1 0x28 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO2_1. 0x0 DSR_ Select function DSR. 0x1 SCK1 Select function SCK1 (function not available on all parts). 0x2 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO2_10 I/O configuration for pin PIO2_10 0x58 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO2_10. 0x0 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO2_11 I/O configuration for pin PIO2_11/SCK 0x70 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO2_11. 0x0 SCK Selects function SCK0 (only if pin PIO2_11/SCK0 selected in Table 139) 0x1 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO2_2 I/O configuration for pin PIO2_2/DCD/MISO1 0x5C read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO2_2. 0x0 DCD_ Select function DCD. 0x1 MISO Select function MISO1 (function not available on all parts). 0x2 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO2_3 I/O configuration for pin PIO2_3/RI/MOSI1 0x8C read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO2_3. 0x0 RI_ Selects function RI. 0x1 MOS Selects function MOSI1 (function not available on all parts). 0x2 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO2_4 I/O configuration for pin PIO2_4 0x40 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO2_4. 0x0 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO2_5 I/O configuration for pin PIO2_5 0x44 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO2_5. 0x0 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO2_6 I/O configuration for pin PIO2_6 0x0 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO2_6. 0x0 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control). 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO2_7 I/O configuration for pin PIO2_7 0x20 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO2_7. 0x0 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO2_8 I/O configuration for pin PIO2_8 0x24 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO2_8. 0x0 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO2_9 I/O configuration for pin PIO2_9 0x54 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO2_9. 0x0 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO3_0 I/O configuration for pin PIO3_0/DTR 0x84 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO3_0. 0x0 DTR Selects function DTR (function not available on all parts). 0x1 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO3_1 I/O configuration for pin PIO3_1/DSR 0x88 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO3_1. 0x0 DSR Selects function DSR (function not available on all parts, must also be configured in the corresponding DSR_LOC register). 0x1 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO3_2 I/O configuration for pin PIO3_2/DCD 0x9C read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO3_2. 0x0 DCD Selects function DCD (function not available on all parts, must also be configured in the corresponding DCD_LOC register). 0x1 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO3_3 I/O configuration for pin PIO3_3/RI 0xAC read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO3_3. 0x0 RI_ Selects function RI (function not available on all parts, must also be configured in the corresponding RI_LOC register). 0x1 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO3_4 I/O configuration for pin PIO3_4 0x3C read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO3_4. 0x0 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 PIO3_5 I/O configuration for pin PIO3_5 0x48 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM PIO Selects function PIO3_5. 0x0 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 RESET_PIO0_0 I/O configuration for pin RESET/PIO0_0 0xC read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM RES Selects function RESET. 0x0 PIO Selects function PIO0_0. 0x1 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 RI_LOC RI pin location register 0xBC read-write n 0x0 0x0 RESERVED Reserved. 2 32 RILOC Selects pin location for RI pin (this register is only used for parts LPC1311/01 and LPC1313/01) 0 2 ENUM SELECTS_RI_FUNCTION_ Selects RI function in pin location PIO3_3/RI. 0x1 SELECTS_RI_FUNCTION_ Selects RI function in pin location PIO3_3/RI. 0x1 RESERVED_ Reserved. 0x3 RESERVED_ Reserved. 0x3 R_PIO0_11 I/O configuration for pin R/PIO0_11/AD0/CT32B0_MAT3 0x74 read-write n 0x0 0x0 ADMODE Selects Analog/Digital mode 7 8 ENUM ANALOG_INPUT_MODE Analog input mode 0 DIGITAL_FUNCTIONAL_M Digital functional mode 1 FUNC Selects pin function. All other values are reserved. 0 3 ENUM R_ Selects function R. This function is reserved. Select one of the alternate functions below. 0x0 PIO Selects function PIO0_11. 0x1 AD0 Selects function AD0. 0x2 CT3 Selects function CT32B0_MAT3. 0x3 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 8 10 RESERVED Reserved 11 32 R_PIO1_0 I/O configuration for pin R/PIO1_0/AD1/ CT32B1_CAP0 0x78 read-write n 0x0 0x0 ADMODE Selects Analog/Digital mode 7 8 ENUM ANALOG_INPUT_MODE Analog input mode 0 DIGITAL_FUNCTIONAL_M Digital functional mode 1 FUNC Selects pin function. All other values are reserved. 0 3 ENUM R_ Selects function R. This function is reserved. Select one of the alternate functions below. 0x0 PIO Selects function PIO1_0. 0x1 AD1 Selects function AD1. 0x2 CT3 Selects function CT32B1_CAP0. 0x3 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 8 10 RESERVED Reserved 11 32 R_PIO1_1 I/O configuration for pin R/PIO1_1/AD2/CT32B1_MAT0 0x7C read-write n 0x0 0x0 ADMODE Selects Analog/Digital mode 7 8 ENUM ANALOG_INPUT_MODE Analog input mode 0 DIGITAL_FUNCTIONAL_M Digital functional mode 1 FUNC Selects pin function. All other values are reserved. 0 3 ENUM R_ Selects function R. This function is reserved. Select one of the alternate functions below. 0x0 PIO Selects function PIO1_1. 0x1 AD2 Selects function AD2. 0x2 CT3 Selects function CT32B1_MAT0. 0x3 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 8 10 RESERVED Reserved 11 32 R_PIO1_2 I/O configuration for pin R/PIO1_2/AD3/ CT32B1_MAT1 0x80 read-write n 0x0 0x0 ADMODE Selects Analog/Digital mode 7 8 ENUM ANALOG_INPUT_MODE Analog input mode 0 DIGITAL_FUNCTIONAL_M Digital functional mode 1 FUNC Selects pin function. All other values are reserved. 0 3 ENUM R_ Selects function R. This function is reserved. Select one of the alternate functions below. 0x0 PIO Selects function PIO1_2. 0x1 AD3 Selects function AD3. 0x2 CT3 Selects function CT32B1_MAT1. 0x3 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 8 10 RESERVED Reserved 11 32 SCK0_LOC SCK0 pin location register 0xB0 read-write n 0x0 0x0 RESERVED Reserved 2 32 SCKLOC Selects pin location for SCK0 pin. 0 2 ENUM SELECTS_SCK0_FUNCTIO Selects SCK0 function for pin PIO0_6/USB_CONNECT/SCK0 (see Table 114). 0x2 SELECTS_SCK0_FUNCTIO Selects SCK0 function for pin PIO0_6/USB_CONNECT/SCK0 (see Table 114). 0x2 SELECTS_SCK0_FUNCTIO Selects SCK0 function for pin PIO0_6/USB_CONNECT/SCK0 (see Table 114). 0x2 RESERVED_ Reserved. 0x3 SWCLK_PIO0_10 I/O configuration for pin SWCLK/PIO0_10/ SCK/CT16B0_MAT2 0x68 read-write n 0x0 0x0 FUNC Selects pin function. All other values are reserved. 0 3 ENUM SWC Selects function SWCLK. 0x0 PIO Selects function PIO0_10. 0x1 SCK Selects function SCK0 (only if pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 selected in Table 139). 0x2 CT1 Selects function CT16B0_MAT2. 0x3 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 11 32 SWDIO_PIO1_3 I/O configuration for pin SWDIO/PIO1_3/AD4/ CT32B1_MAT2 0x90 read-write n 0x0 0x0 ADMODE Selects Analog/Digital mode 7 8 ENUM ANALOG_INPUT_MODE Analog input mode 0 DIGITAL_FUNCTIONAL_M Digital functional mode 1 FUNC Selects pin function. All other values are reserved. 0 3 ENUM SWD Selects function SWDIO. 0x0 PIO Selects function PIO1_3. 0x1 AD4 Selects function AD4. 0x2 CT3 Selects function CT32B1_MAT2. 0x3 HYS Hysteresis 5 6 ENUM DISABLE Disable 0 ENABLE Enable 1 MODE Selects function mode (on-chip pull-up/pull-down resistor control) 3 5 ENUM INACTIVE_NO_PULL_DO Inactive (no pull-down/pull-up resistor enabled) 0x0 PULL_DOWN_RESISTOR_E Pull-down resistor enabled 0x1 PULL_UP_RESISTOR_ENA Pull-up resistor enabled 0x2 REPEATER_MODE Repeater mode 0x3 OD Selects pseudo open-drain mode. 10 11 ENUM STANDARD_GPIO_OUTPUT Standard GPIO output 0 OPEN_DRAIN_OUTPUT Open-drain output 1 RESERVED Reserved 11 32 RESERVED Reserved 8 10 RESERVED Reserved 11 32 PMU Power Management Unit (PMU) PMU 0x0 0x0 0xFFF registers n GPREG0 General purpose register 0x4 -1 read-write n 0x0 0x0 GPDATA Data retained during Deep power-down mode. 0 32 GPREG1 General purpose register 0x8 -1 read-write n 0x0 0x0 GPDATA Data retained during Deep power-down mode. 0 32 GPREG2 General purpose register 0xC -1 read-write n 0x0 0x0 GPDATA Data retained during Deep power-down mode. 0 32 GPREG3 General purpose register 0x10 -1 read-write n 0x0 0x0 GPDATA Data retained during Deep power-down mode. 0 32 GPREG4 General purpose register 4 0x14 read-write n 0x0 0x0 GPDATA Data retained during Deep power-down mode. 11 32 RESERVED Reserved. Do not write ones to this bit. 0 10 WAKEUPHYS WAKEUP pin hysteresis enable 10 11 ENUM DISABLED Hysteresis for WAKUP pin disabled. 0 ENABLED Hysteresis for WAKEUP pin enabled. 1 PCON Power control register 0x0 read-write n 0x0 0x0 DPDEN Deep power-down mode enable 1 2 ENUM SLEEP_DEEPSLEEP ARM WFI will enter Sleep or Deep-sleep mode (clock to ARM Cortex-M3 core turned off). 0 DEEPPOWERDOWN ARM WFI will enter Deep-power down mode (ARM Cortex-M3 core powered-down). 1 DPDFLAG Deep power-down flag 11 12 ENUM NO_DEEPPOWERDOWN Read: Deep power-down mode not entered. Write: No effect. 0 DEEPPOWERDOWN Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. 1 RESERVED Reserved. Do not write ones to this bit. 12 32 RESERVED Reserved. Do not write ones to this bit. 2 8 RESERVED Reserved. Do not write ones to this bit. 9 11 RESERVED Reserved. Do not write ones to this bit. 12 32 SLEEPFLAG Sleep mode flag 8 9 ENUM NO_POWER_DOWN_ Read: No power-down mode entered. LPC13xx is in Run mode. Write: No effect. 0 POWERDOWN Read: Sleep/Deep-sleep or Deep power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. 1 SSP0 SSP0/1 SSP0 0x0 0x0 0xFFF registers n SSP0 45 CPSR Clock Prescale Register. 0x10 read-write n 0x0 0x0 CPSDVSR This even value between 2 and 254, by which SSP_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. 0 8 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 8 32 CR0 Control Register 0. Selects the serial clock rate, bus type, and data size. 0x0 read-write n 0x0 0x0 CPHA Clock Out Phase. This bit is only used in SPI mode. 7 8 ENUM FIRSTCLOCK SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. 0 SECONDCLOK SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. 1 CPOL Clock Out Polarity. This bit is only used in SPI mode. 6 7 ENUM LOW SSP controller maintains the bus clock low between frames. 0 HIGH SSP controller maintains the bus clock high between frames. 1 DSS Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. 0 4 ENUM 4_BIT_TRANSFER 4-bit transfer 0x3 5_BIT_TRANSFER 5-bit transfer 0x4 6_BIT_TRANSFER 6-bit transfer 0x5 7_BIT_TRANSFER 7-bit transfer 0x6 8_BIT_TRANSFER 8-bit transfer 0x7 9_BIT_TRANSFER 9-bit transfer 0x8 10_BIT_TRANSFER 10-bit transfer 0x9 11_BIT_TRANSFER 11-bit transfer 0xA 12_BIT_TRANSFER 12-bit transfer 0xB 13_BIT_TRANSFER 13-bit transfer 0xC 14_BIT_TRANSFER 14-bit transfer 0xD 15_BIT_TRANSFER 15-bit transfer 0xE 16_BIT_TRANSFER 16-bit transfer 0xF FRF Frame Format. 4 6 ENUM SPI SPI 0x0 TI TI 0x1 MICROWIRE Microwire 0x2 THIS_COMBINATION_IS_ This combination is not supported and should not be used. 0x3 RESERVED Reserved. 16 32 SCR Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR x [SCR+1]). 8 16 CR1 Control Register 1. Selects master/slave and other modes. 0x4 read-write n 0x0 0x0 LBM Loop Back Mode. 0 1 ENUM NORMAL During normal operation. 0 OUTPUT Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). 1 MS Master/Slave Mode.This bit can only be written when the SSE bit is 0. 2 3 ENUM MASTER The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. 0 SLAVE The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 SOD Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). 3 4 SSE SSP Enable. 1 2 ENUM DISABLED The SSP controller is disabled. 0 ENABLED The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit. 1 DR Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. 0x8 read-write n 0x0 0x0 modify DATA Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s. 0 16 RESERVED Reserved. 16 32 ICR SSPICR Interrupt Clear Register. 0x20 write-only n 0x0 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 2 32 RORIC Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. 0 1 RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read-bit for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). 1 2 IMSC Interrupt Mask Set and Clear Register. 0x14 read-write n 0x0 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. 0 1 RTIM Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). 1 2 RXIM Software should set this bit to enable interrupt when the Rx FIFO is at least half full. 2 3 TXIM Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. 3 4 MIS Masked Interrupt Status Register. 0x1C read-only n 0x0 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. 0 1 RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). 1 2 RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. 2 3 TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. 3 4 RIS Raw Interrupt Status Register. 0x18 read-only n 0x0 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 RORRIS This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. 0 1 RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). 1 2 RXRIS This bit is 1 if the Rx FIFO is at least half full. 2 3 TXRIS This bit is 1 if the Tx FIFO is at least half empty. 3 4 SR Status Register. 0xC read-only n 0x0 0x0 BSY Busy. This bit is 0 if the SSP0 controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. 4 5 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 5 32 RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. 3 4 RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. 2 3 TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 0 1 TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1 2 SSP1 SSP0/1 SSP0 0x0 0x0 0xFFF registers n SSP1 57 CPSR Clock Prescale Register. 0x10 read-write n 0x0 0x0 CPSDVSR This even value between 2 and 254, by which SSP_PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0. 0 8 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 8 32 CR0 Control Register 0. Selects the serial clock rate, bus type, and data size. 0x0 read-write n 0x0 0x0 CPHA Clock Out Phase. This bit is only used in SPI mode. 7 8 ENUM FIRSTCLOCK SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line. 0 SECONDCLOK SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line. 1 CPOL Clock Out Polarity. This bit is only used in SPI mode. 6 7 ENUM LOW SSP controller maintains the bus clock low between frames. 0 HIGH SSP controller maintains the bus clock high between frames. 1 DSS Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used. 0 4 ENUM 4_BIT_TRANSFER 4-bit transfer 0x3 5_BIT_TRANSFER 5-bit transfer 0x4 6_BIT_TRANSFER 6-bit transfer 0x5 7_BIT_TRANSFER 7-bit transfer 0x6 8_BIT_TRANSFER 8-bit transfer 0x7 9_BIT_TRANSFER 9-bit transfer 0x8 10_BIT_TRANSFER 10-bit transfer 0x9 11_BIT_TRANSFER 11-bit transfer 0xA 12_BIT_TRANSFER 12-bit transfer 0xB 13_BIT_TRANSFER 13-bit transfer 0xC 14_BIT_TRANSFER 14-bit transfer 0xD 15_BIT_TRANSFER 15-bit transfer 0xE 16_BIT_TRANSFER 16-bit transfer 0xF FRF Frame Format. 4 6 ENUM SPI SPI 0x0 TI TI 0x1 MICROWIRE Microwire 0x2 THIS_COMBINATION_IS_ This combination is not supported and should not be used. 0x3 RESERVED Reserved. 16 32 SCR Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR x [SCR+1]). 8 16 CR1 Control Register 1. Selects master/slave and other modes. 0x4 read-write n 0x0 0x0 LBM Loop Back Mode. 0 1 ENUM NORMAL During normal operation. 0 OUTPUT Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively). 1 MS Master/Slave Mode.This bit can only be written when the SSE bit is 0. 2 3 ENUM MASTER The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line. 0 SLAVE The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 SOD Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO). 3 4 SSE SSP Enable. 1 2 ENUM DISABLED The SSP controller is disabled. 0 ENABLED The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit. 1 DR Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. 0x8 read-write n 0x0 0x0 modify DATA Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bit, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bit, the data is right-justified in this field with higher order bits filled with 0s. 0 16 RESERVED Reserved. 16 32 ICR SSPICR Interrupt Clear Register. 0x20 write-only n 0x0 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 2 32 RORIC Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt. 0 1 RTIC Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read-bit for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). 1 2 IMSC Interrupt Mask Set and Clear Register. 0x14 read-write n 0x0 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. 0 1 RTIM Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). 1 2 RXIM Software should set this bit to enable interrupt when the Rx FIFO is at least half full. 2 3 TXIM Software should set this bit to enable interrupt when the Tx FIFO is at least half empty. 3 4 MIS Masked Interrupt Status Register. 0x1C read-only n 0x0 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled. 0 1 RTMIS This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). 1 2 RXMIS This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled. 2 3 TXMIS This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled. 3 4 RIS Raw Interrupt Status Register. 0x18 read-only n 0x0 0x0 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 32 RORRIS This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs. 0 1 RTRIS This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR x [SCR+1]). 1 2 RXRIS This bit is 1 if the Rx FIFO is at least half full. 2 3 TXRIS This bit is 1 if the Tx FIFO is at least half empty. 3 4 SR Status Register. 0xC read-only n 0x0 0x0 BSY Busy. This bit is 0 if the SSP0 controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty. 4 5 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 5 32 RFF Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not. 3 4 RNE Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not. 2 3 TFE Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not. 0 1 TNF Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not. 1 2 SYSCON System configuration SYSCON 0x0 0x0 0xFFF registers n PIO0_0 0 PIO0_1 1 PIO0_2 2 PIO0_3 3 PIO0_4 4 PIO0_5 5 PIO0_6 6 PIO0_7 7 PIO0_8 8 PIO0_9 9 PIO0_10 10 PIO0_11 11 PIO1_0 12 PIO1_1 13 PIO1_2 14 PIO1_3 15 PIO1_4 16 PIO1_5 17 PIO1_6 18 PIO1_7 19 PIO1_8 20 PIO1_9 21 PIO1_10 22 PIO1_11 23 PIO2_0 24 PIO2_1 25 PIO2_2 26 PIO2_3 27 PIO2_4 28 PIO2_5 29 PIO2_6 30 PIO2_7 31 PIO2_8 32 PIO2_9 33 PIO2_10 34 PIO2_11 35 PIO3_0 36 PIO3_1 37 PIO3_2 38 PIO3_3 39 BOD 51 BODCTRL BOD control 0x150 read-write n 0x0 0x0 BODINTVAL BOD interrupt level. Trip values x/y refer to the LPC1300/LPC1300L series. 2 4 ENUM THE_INTERRUPT_ASSERT The interrupt assertion threshold voltage is 2.87 V/2.80 V the interrupt de-assertion threshold voltage is 2.98 V/2.90 V. 0x3 THE_INTERRUPT_ASSERT The interrupt assertion threshold voltage is 2.87 V/2.80 V the interrupt de-assertion threshold voltage is 2.98 V/2.90 V. 0x3 THE_INTERRUPT_ASSERT The interrupt assertion threshold voltage is 2.87 V/2.80 V the interrupt de-assertion threshold voltage is 2.98 V/2.90 V. 0x3 THE_INTERRUPT_ASSERT The interrupt assertion threshold voltage is 2.87 V/2.80 V the interrupt de-assertion threshold voltage is 2.98 V/2.90 V. 0x3 BODRSTENA BOD reset enable 4 5 ENUM DISABLE_RESET_FUNCTI Disable reset function. 0 ENABLE_RESET_FUNCTIO Enable reset function. 1 BODRSTLEV BOD reset level. Trip values x/y refer to the LPC1300/LPC1300L series. 0 2 ENUM THE_RESET_ASSERTION_ The reset assertion threshold voltage is -/2.63 V the reset de-assertion threshold voltage is -/2.71 V. 0x3 THE_RESET_ASSERTION_ The reset assertion threshold voltage is -/2.63 V the reset de-assertion threshold voltage is -/2.71 V. 0x3 THE_RESET_ASSERTION_ The reset assertion threshold voltage is -/2.63 V the reset de-assertion threshold voltage is -/2.71 V. 0x3 THE_RESET_ASSERTION_ The reset assertion threshold voltage is -/2.63 V the reset de-assertion threshold voltage is -/2.71 V. 0x3 RESERVED Reserved 5 32 CLKOUTCLKSEL CLKOUT clock source select 0xE0 read-write n 0x0 0x0 RESERVED Reserved 2 32 SEL CLKOUT clock source 0 2 ENUM IRC_OSCILLATOR IRC oscillator 0x0 SYSTEM_OSCILLATOR System oscillator 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator 0x2 MAIN_CLOCK Main clock 0x3 CLKOUTDIV CLKOUT clock divider 0xE8 read-write n 0x0 0x0 DIV Clock divider values. 0: Disable CLKOUT. 1: Divide by 1. to 255: Divide by 255. 0 8 RESERVED Reserved 8 32 CLKOUTUEN CLKOUT clock source update enable 0xE4 read-write n 0x0 0x0 ENA Enable CLKOUT clock source update 0 1 ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved 1 32 DEVICE_ID Device ID 0x3F4 read-only n 0x0 0x0 DEVICEID Device ID for LPC13xx parts: 0x2C42 502B = LPC1311FHN33 0x2C40 102B = LPC1313FHN33 0x2C40 102B = LPC1313FBD48 0x3D01 402B = LPC1342FHN33 0x3D00 002B = LPC1343FHN33 0x3D00 002B = LPC1343FBD48 0x1816 902B = LPC1311FHN33/01 0x1830 102B = LPC1313FHN33/01 0x1830 102B = LPC1313FBD48/01 0 32 IRCCTRL IRC control 0x28 read-write n 0x0 0x0 RESERVED Reserved 8 32 TRIM Trim value 0 8 MAINCLKSEL Main clock source select 0x70 read-write n 0x0 0x0 RESERVED Reserved 2 32 SEL Clock source for main clock 0 2 ENUM IRC_OSCILLATOR IRC oscillator 0x0 INPUT_CLOCK_TO_SYSTE Input clock to system PLL 0x1 WDT_OSCILLATOR WDT oscillator 0x2 SYSTEM_PLL_CLOCK_OUT System PLL clock out 0x3 MAINCLKUEN Main clock source update enable 0x74 read-write n 0x0 0x0 ENA Enable main clock source update 0 1 ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved 1 32 PDAWAKECFG Power-down states after wake-up from Deep-sleep mode 0x234 read-write n 0x0 0x0 ADC_PD ADC wake-up configuration 4 5 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 BOD_PD BOD wake-up configuration 3 4 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 FIXEDVAL0 Reserved. Always write this bit as 0. 9 10 FIXEDVAL1 Reserved. Always write this bit as 1. 11 12 FIXEDVAL2 Reserved. Always write this bit as 0. 12 13 FIXEDVAL3 Reserved. Always write these bits as 111. 13 16 FLASH_PD Flash wake-up configuration 2 3 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IRCOUT_PD IRC oscillator output wake-up configuration 0 1 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IRC_PD IRC oscillator power-down wake-up configuration 1 2 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved 12 32 SYSOSC_PD System oscillator wake-up configuration 5 6 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSPLL_PD System PLL wake-up configuration 7 8 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 USBPAD_PD USB pad wake-up configuration 10 11 ENUM USB_PHY_POWERED USB PHY powered 0 USB_PHY_POWERED_DOWN USB PHY powered down 1 USBPLL_PD USB PLL wake-up configuration 8 9 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 WDTOSC_PD Watchdog oscillator wake-up configuration 6 7 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 PDRUNCFG Power-down configuration register 0x238 read-write n 0x0 0x0 ADC_PD ADC power-down 4 5 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 BOD_PD BOD power-down 3 4 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 FIXEDVAL0 Reserved. Always write this bit as 0. 9 10 FIXEDVAL1 Reserved. Always write this bit as 1. 11 12 FLASH_PD Flash power-down 2 3 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IRCOUT_PD IRC oscillator output power-down 0 1 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 IRC_PD IRC oscillator power-down 1 2 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 RESERVED Reserved 12 32 SYSOSC_PD System oscillator power-down[1] 5 6 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 SYSPLL_PD System PLL power-down 7 8 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 USBPAD_PD USB pad power-down configuration 10 11 ENUM USB_PHY_POWERED USB PHY powered 0 USB_PHY_POWERED_DOWN USB PHY powered down (suspend mode) 1 USBPLL_PD USB PLL power-down 8 9 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 WDTOSC_PD Watchdog oscillator power-down 6 7 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 PDSLEEPCFG Power-down states in Deep-sleep mode 0x230 read-write n 0x0 0x0 BOD_PD BOD power-down control in Deep-sleep mode, see Table 49. 3 4 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 FIXEDVAL0 Reserved. Always write these bits as 111. 0 3 FIXEDVAL1 Reserved. Always write these bits as 11. 4 6 FIXEDVAL2 Reserved. Always write these bits as 11111. 7 12 RESERVED Reserved 12 32 WDTOSC_PD Watchdog oscillator power control in Deep-sleep mode, see Table 49. 6 7 ENUM POWERED Powered 0 POWERED_DOWN Powered down 1 PIOPORCAP0 POR captured PIO status 0 0x100 read-only n 0x0 0x0 CAPPIO0_0 Raw reset status input PIO0_11 to PIO0_0 0 1 CAPPIO0_1 Raw reset status input PIO0_11 to PIO0_0 1 2 CAPPIO0_10 Raw reset status input PIO0_11 to PIO0_0 10 11 CAPPIO0_11 Raw reset status input PIO0_11 to PIO0_0 11 12 CAPPIO0_2 Raw reset status input PIO0_11 to PIO0_0 2 3 CAPPIO0_3 Raw reset status input PIO0_11 to PIO0_0 3 4 CAPPIO0_4 Raw reset status input PIO0_11 to PIO0_0 4 5 CAPPIO0_5 Raw reset status input PIO0_11 to PIO0_0 5 6 CAPPIO0_6 Raw reset status input PIO0_11 to PIO0_0 6 7 CAPPIO0_7 Raw reset status input PIO0_11 to PIO0_0 7 8 CAPPIO0_8 Raw reset status input PIO0_11 to PIO0_0 8 9 CAPPIO0_9 Raw reset status input PIO0_11 to PIO0_0 9 10 CAPPIO1_0 Raw reset status input PIO1_11 to PIO1_0 12 13 CAPPIO1_1 Raw reset status input PIO1_11 to PIO1_0 13 14 CAPPIO1_10 Raw reset status input PIO1_11 to PIO1_0 22 23 CAPPIO1_11 Raw reset status input PIO1_11 to PIO1_0 23 24 CAPPIO1_2 Raw reset status input PIO1_11 to PIO1_0 14 15 CAPPIO1_3 Raw reset status input PIO1_11 to PIO1_0 15 16 CAPPIO1_4 Raw reset status input PIO1_11 to PIO1_0 16 17 CAPPIO1_5 Raw reset status input PIO1_11 to PIO1_0 17 18 CAPPIO1_6 Raw reset status input PIO1_11 to PIO1_0 18 19 CAPPIO1_7 Raw reset status input PIO1_11 to PIO1_0 19 20 CAPPIO1_8 Raw reset status input PIO1_11 to PIO1_0 20 21 CAPPIO1_9 Raw reset status input PIO1_11 to PIO1_0 21 22 CAPPIO2_0 Raw reset status input PIO2_7 to PIO2_0 24 25 CAPPIO2_1 Raw reset status input PIO2_7 to PIO2_0 25 26 CAPPIO2_2 Raw reset status input PIO2_7 to PIO2_0 26 27 CAPPIO2_3 Raw reset status input PIO2_7 to PIO2_0 27 28 CAPPIO2_4 Raw reset status input PIO2_7 to PIO2_0 28 29 CAPPIO2_5 Raw reset status input PIO2_7 to PIO2_0 29 30 CAPPIO2_6 Raw reset status input PIO2_7 to PIO2_0 30 31 CAPPIO2_7 Raw reset status input PIO2_7 to PIO2_0 31 32 PIOPORCAP1 POR captured PIO status 1 0x104 read-only n 0x0 0x0 CAPPIO2_10 Raw reset status input PIO2_10 2 3 CAPPIO2_11 Raw reset status input PIO2_11 3 4 CAPPIO2_8 Raw reset status input PIO2_8 0 1 CAPPIO2_9 Raw reset status input PIO2_9 1 2 CAPPIO3_0 Raw reset status input PIO3_0 4 5 CAPPIO3_1 Raw reset status input PIO3_1 5 6 CAPPIO3_2 Raw reset status input PIO3_2 6 7 CAPPIO3_3 Raw reset status input PIO3_3 7 8 CAPPIO3_4 Raw reset status input PIO3_4 8 9 CAPPIO3_5 Raw reset status input PIO3_5 9 10 RESERVED Reserved 10 32 PRESETCTRL Peripheral reset control 0x4 read-write n 0x0 0x0 I2C_RST_N I2C reset control 1 2 ENUM RESET_I2C_ Reset I2C. 0 DE_ASSET_I2C_RESET_ De-asset I2C reset. 1 RESERVED Reserved 23 32 SSP0_RST_N SSP0 reset control 0 1 ENUM RESET_SSP0_ Reset SSP0. 0 DE_ASSERT_SSP0_RESET De-assert SSP0 reset. 1 SSP1_RST_N SPISP1 reset control 2 3 ENUM RESET_THE_SPISP1_ Reset the SPISP1. 0 DE_ASSERT_SPISP1_RES De-assert SPISP1 reset. 1 SSP0CLKDIV SSP clock divder 0x94 read-write n 0x0 0x0 DIV SSP_PCLK clock divider values. 0: Disable SSP0_PCLK. 1: Divide by 1. to 255: Divide by 255. 0 8 RESERVED Reserved 8 32 SSP1CLKDIV SPISP1 clock divder 0x9C read-write n 0x0 0x0 DIV SSP1_PCLK clock divider values 0: Disable SSP1_PCLK. 1: Divide by 1. to 255: Divide by 255. 0 8 RESERVED Reserved 8 32 STARTAPRP0 Start logic edge control register 0 bottom 32 interrupts 0x200 -1 read-write n 0x0 0x0 APRPIO0_0 Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge. 0 1 APRPIO0_1 Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge. 1 2 APRPIO0_10 Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge. 10 11 APRPIO0_11 Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge. 11 12 APRPIO0_2 Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge. 2 3 APRPIO0_3 Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge. 3 4 APRPIO0_4 Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge. 4 5 APRPIO0_5 Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge. 5 6 APRPIO0_6 Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge. 6 7 APRPIO0_7 Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge. 7 8 APRPIO0_8 Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge. 8 9 APRPIO0_9 Edge select for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Falling edge. 1 = Rising edge. 9 10 APRPIO1_0 Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge. 12 13 APRPIO1_1 Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge. 13 14 APRPIO1_10 Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge. 22 23 APRPIO1_11 Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge. 23 24 APRPIO1_2 Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge. 14 15 APRPIO1_3 Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge. 15 16 APRPIO1_4 Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge. 16 17 APRPIO1_5 Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge. 17 18 APRPIO1_6 Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge. 18 19 APRPIO1_7 Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge. 19 20 APRPIO1_8 Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge. 20 21 APRPIO1_9 Edge select for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Falling edge. 1 = Rising edge. 21 22 APRPIO2_0 Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge. 24 25 APRPIO2_1 Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge. 25 26 APRPIO2_2 Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge. 26 27 APRPIO2_3 Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge. 27 28 APRPIO2_4 Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge. 28 29 APRPIO2_5 Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge. 29 30 APRPIO2_6 Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge. 30 31 APRPIO2_7 Edge select for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Falling edge. 1 = Rising edge. 31 32 STARTAPRP1 Start logic edge control register 1 top 8 interrupts 0x210 -1 read-write n 0x0 0x0 APRPIO2_10 Edge select for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Falling edge. 1 = Rising edge. 2 3 APRPIO2_11 Edge select for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Falling edge. 1 = Rising edge. 3 4 APRPIO2_8 Edge select for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Falling edge. 1 = Rising edge. 0 1 APRPIO2_9 Edge select for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Falling edge. 1 = Rising edge. 1 2 APRPIO3_0 Edge select for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Falling edge. 1 = Rising edge. 4 5 APRPIO3_1 Edge select for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Falling edge. 1 = Rising edge. 5 6 APRPIO3_2 Edge select for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Falling edge. 1 = Rising edge. 6 7 APRPIO3_3 Edge select for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Falling edge. 1 = Rising edge. 7 8 RESERVED Reserved 8 32 STARTERP0 Start logic signal enable register 0 bottom 32 interrupts 0x204 -1 read-write n 0x0 0x0 ERPIO0_0 Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled. 0 1 ERPIO0_1 Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled. 1 2 ERPIO0_10 Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled. 10 11 ERPIO0_11 Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled. 11 12 ERPIO0_2 Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled. 2 3 ERPIO0_3 Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled. 3 4 ERPIO0_4 Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled. 4 5 ERPIO0_5 Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled. 5 6 ERPIO0_6 Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled. 6 7 ERPIO0_7 Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled. 7 8 ERPIO0_8 Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled. 8 9 ERPIO0_9 Enable start signal for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Disabled. 1 = Enabled. 9 10 ERPIO1_0 Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled. 12 13 ERPIO1_1 Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled. 13 14 ERPIO1_10 Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled. 22 23 ERPIO1_11 Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled. 23 24 ERPIO1_2 Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled. 14 15 ERPIO1_3 Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled. 15 16 ERPIO1_4 Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled. 16 17 ERPIO1_5 Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled. 17 18 ERPIO1_6 Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled. 18 19 ERPIO1_7 Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled. 19 20 ERPIO1_8 Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled. 20 21 ERPIO1_9 Enable start signal for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Disabled. 1 = Enabled. 21 22 ERPIO2_0 Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled. 24 25 ERPIO2_1 Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled. 25 26 ERPIO2_2 Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled. 26 27 ERPIO2_3 Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled. 27 28 ERPIO2_4 Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled. 28 29 ERPIO2_5 Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled. 29 30 ERPIO2_6 Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled. 30 31 ERPIO2_7 Enable start signal for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Disabled. 1 = Enabled. 31 32 STARTERP1 Start logic signal enable register 1 top 8 interrupts 0x214 -1 read-write n 0x0 0x0 ERPIO2_10 Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled. 2 3 ERPIO2_11 Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled. 3 4 ERPIO2_8 Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled. 0 1 ERPIO2_9 Enable start signal for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Disabled. 1 = Enabled. 1 2 ERPIO3_0 Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled. 4 5 ERPIO3_1 Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled. 5 6 ERPIO3_2 Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled. 6 7 ERPIO3_3 Enable start signal for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Disabled. 1 = Enabled. 7 8 RESERVED Reserved 8 32 STARTRSRP0CLR Start logic reset register 0 bottom 32 interrupts 0x208 -1 write-only n 0x0 0x0 RSRPIO0_0 Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal. 0 1 RSRPIO0_1 Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal. 1 2 RSRPIO0_10 Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal. 10 11 RSRPIO0_11 Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal. 11 12 RSRPIO0_2 Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal. 2 3 RSRPIO0_3 Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal. 3 4 RSRPIO0_4 Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal. 4 5 RSRPIO0_5 Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal. 5 6 RSRPIO0_6 Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal. 6 7 RSRPIO0_7 Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal. 7 8 RSRPIO0_8 Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal. 8 9 RSRPIO0_9 Start signal reset for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = Do nothing. 1 = Write: reset start signal. 9 10 RSRPIO1_0 Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal. 12 13 RSRPIO1_1 Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal. 13 14 RSRPIO1_10 Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal. 22 23 RSRPIO1_11 Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal. 23 24 RSRPIO1_2 Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal. 14 15 RSRPIO1_3 Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal. 15 16 RSRPIO1_4 Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal. 16 17 RSRPIO1_5 Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal. 17 18 RSRPIO1_6 Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal. 18 19 RSRPIO1_7 Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal. 19 20 RSRPIO1_8 Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal. 20 21 RSRPIO1_9 Start signal reset for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = Do nothing. 1 = Write: reset start signal. 21 22 RSRPIO2_0 Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal. 24 25 RSRPIO2_1 Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal. 25 26 RSRPIO2_2 Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal. 26 27 RSRPIO2_3 Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal. 27 28 RSRPIO2_4 Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal. 28 29 RSRPIO2_5 Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal. 29 30 RSRPIO2_6 Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal. 30 31 RSRPIO2_7 Start signal reset for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = Do nothing. 1 = Write: reset start signal. 31 32 STARTRSRP1CLR Start logic reset register 1 top 8 interrupts 0x218 -1 write-only n 0x0 0x0 RESERVED Reserved 8 32 RSRPIO2_10 Start signal reset for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Do nothing.. 1 = Write: reset start signal. 2 3 RSRPIO2_11 Start signal reset for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Do nothing.. 1 = Write: reset start signal. 3 4 RSRPIO2_8 Start signal reset for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Do nothing.. 1 = Write: reset start signal. 0 1 RSRPIO2_9 Start signal reset for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = Do nothing.. 1 = Write: reset start signal. 1 2 RSRPIO3_0 Start signal reset for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Do nothing.. 1 = Write: reset start signal. 4 5 RSRPIO3_1 Start signal reset for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Do nothing.. 1 = Write: reset start signal. 5 6 RSRPIO3_2 Start signal reset for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Do nothing.. 1 = Write: reset start signal. 6 7 RSRPIO3_3 Start signal reset for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = Do nothing.. 1 = Write: reset start signal. 7 8 STARTSRP0 Start logic status register 0 bottom 32 interrupts 0x20C -1 read-only n 0x0 0x0 SRPIO0_0 Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending. 0 1 SRPIO0_1 Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending. 1 2 SRPIO0_10 Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending. 10 11 SRPIO0_11 Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending. 11 12 SRPIO0_2 Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending. 2 3 SRPIO0_3 Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending. 3 4 SRPIO0_4 Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending. 4 5 SRPIO0_5 Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending. 5 6 SRPIO0_6 Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending. 6 7 SRPIO0_7 Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending. 7 8 SRPIO0_8 Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending. 8 9 SRPIO0_9 Start signal status for start logic input PIO0_n (bit 0 = PIO0_1, ..., bit 11 = PIO0_11). 0 = No start signal received. 1 = Start signal pending. 9 10 SRPIO1_0 Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending. 12 13 SRPIO1_1 Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending. 13 14 SRPIO1_10 Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending. 22 23 SRPIO1_11 Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending. 23 24 SRPIO1_2 Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending. 14 15 SRPIO1_3 Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending. 15 16 SRPIO1_4 Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending. 16 17 SRPIO1_5 Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending. 17 18 SRPIO1_6 Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending. 18 19 SRPIO1_7 Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending. 19 20 SRPIO1_8 Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending. 20 21 SRPIO1_9 Start signal status for start logic input PIO1_n (bit 12 = PIO1_0, ..., bit 23 = PIO1_11). 0 = No start signal received. 1 = Start signal pending. 21 22 SRPIO2_0 Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending. 24 25 SRPIO2_1 Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending. 25 26 SRPIO2_2 Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending. 26 27 SRPIO2_3 Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending. 27 28 SRPIO2_4 Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending. 28 29 SRPIO2_5 Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending. 29 30 SRPIO2_6 Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending. 30 31 SRPIO2_7 Start signal status for start logic input PIO2_n (bit 24 = PIO2_0, ..., bit 31 = PIO2_7). 0 = No start signal received. 1 = Start signal pending. 31 32 STARTSRP1 Start logic status register 1 top 8 interrupts 0x21C -1 read-only n 0x0 0x0 RESERVED Reserved 8 32 SRPIO2_10 Start signal status for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = No start signal received. 1 = Start signal pending. 2 3 SRPIO2_11 Start signal status for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = No start signal received. 1 = Start signal pending. 3 4 SRPIO2_8 Start signal status for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = No start signal received. 1 = Start signal pending. 0 1 SRPIO2_9 Start signal status for start logic input PIO2_n (bit 0 = PIO2_8, ..., bit 3 = PIO2_11). 0 = No start signal received. 1 = Start signal pending. 1 2 SRPIO3_0 Start signal status for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = No start signal received. 1 = Start signal pending. 4 5 SRPIO3_1 Start signal status for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = No start signal received. 1 = Start signal pending. 5 6 SRPIO3_2 Start signal status for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = No start signal received. 1 = Start signal pending. 6 7 SRPIO3_3 Start signal status for start logic input PIO3_n (bit 4 = PIO3_0, ..., bit 7 = PIO3_3). 0 = No start signal received. 1 = Start signal pending. 7 8 SYSAHBCLKCTRL System AHB clock control 0x80 read-write n 0x0 0x0 ADC Enables clock for ADC. 13 14 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CT16B0 Enables clock for 16-bit counter/timer 0. 7 8 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CT16B1 Enables clock for 16-bit counter/timer 1. 8 9 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CT32B0 Enables clock for 32-bit counter/timer 0. 9 10 ENUM DISABLED Disabled 0 ENABLED Enabled 1 CT32B1 Enables clock for 32-bit counter/timer 1. 10 11 ENUM DISABLED Disabled 0 ENABLED Enabled 1 FLASHARRAY Enables clock for flash array access. 4 5 ENUM DISABLED Disabled 0 ENABLED Enabled 1 FLASHREG Enables clock for flash register interface. 3 4 ENUM DISABLED Disabled 0 ENABLED Enabled 1 GPIO Enables clock for GPIO. 6 7 ENUM DISABLED Disabled 0 ENABLED Enabled 1 I2C Enables clock for I2C. 5 6 ENUM DISABLED Disabled 0 ENABLED Enabled 1 IOCON Enables clock for IO configuration block. 16 17 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RAM Enables clock for RAM. 2 3 ENUM DISABLED Disabled 0 ENABLED Enabled 1 RESERVED Reserved 19 32 RESERVED Reserved 19 32 ROM Enables clock for ROM. 1 2 ENUM DISABLED Disabled 0 ENABLED Enabled 1 SSP Enables clock for SSP. 11 12 ENUM DISABLED Disabled 0 ENABLED Enabled 1 SSP1 Enables clock for SPISP1. 18 19 ENUM DISABLE Disable 0 ENABLE Enable 1 SYS Enables clock for AHB to APB bridge, to the AHB matrix, to the Cortex-M3 FCLK and HCLK, to the SysCon, and to the PMU. This bit is read only. 0 1 ENUM RESERVED Reserved 0 ENABLED Enabled 1 UART Enables clock for UART. Note that the UART pins must be configured in the IOCON block before the UART clock can be enabled. 12 13 ENUM DISABLED Disabled 0 ENABLED Enabled 1 USB_REG Enables clock for USB_REG. 14 15 ENUM DISABLED Disabled 0 ENABLED Enabled 1 WDT Enables clock for WDT. 15 16 ENUM DISABLED Disabled 0 ENABLED Enabled 1 SYSAHBCLKDIV System AHB clock divider 0x78 read-write n 0x0 0x0 DIV System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. 0 8 RESERVED Reserved 8 32 SYSMEMREMAP System memory remap 0x0 read-write n 0x0 0x0 MAP System memory remap 0 2 ENUM BOOT_LOADER_MODE_IN Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 0x0 USER_RAM_MODE_INTER User RAM Mode. Interrupt vectors are re-mapped to Static RAM. 0x1 USER_FLASH_MODE_INT User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. 0x2 RESERVED Reserved 2 32 SYSOSCCTRL System oscillator control 0x20 read-write n 0x0 0x0 BYPASS Bypass system oscillator 0 1 ENUM OSCILLATOR_IS_NOT_BY Oscillator is not bypassed. 0 BYPASS_ENABLED_PLL_ Bypass enabled. PLL input (sys_osc_clk) is fed directly from the XTALIN and XTALOUT pins. 1 FREQRANGE Determines frequency range for Low-power oscillator. 1 2 ENUM 1__20_MHZ_FREQUENCY 1 - 20 MHz frequency range. 0 15__25_MHZ_FREQUENC 15 - 25 MHz frequency range 1 RESERVED Reserved 2 32 SYSPLLCLKSEL System PLL clock source select 0x40 read-write n 0x0 0x0 RESERVED Reserved 2 32 SEL System PLL clock source 0 2 ENUM IRC_OSCILLATOR IRC oscillator 0x0 SYSTEM_OSCILLATOR System oscillator 0x1 RESERVED Reserved 0x3 RESERVED Reserved 0x3 SYSPLLCLKUEN System PLL clock source update enable 0x44 read-write n 0x0 0x0 ENA Enable system PLL clock source update 0 1 ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved 1 32 SYSPLLCTRL System PLL control 0x8 read-write n 0x0 0x0 MSEL Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32. 0 5 PSEL Post divider ratio P. The division ratio is 2 x P. 5 7 ENUM P_EQ_1 P = 1 0x0 P_EQ_2 P = 2 0x1 P_EQ_4 P = 4 0x2 P_EQ_8 P = 8 0x3 RESERVED Reserved. Do not write ones to reserved bits. 7 32 SYSPLLSTAT System PLL status 0xC read-only n 0x0 0x0 LOCK PLL lock status 0 1 ENUM PLL_NOT_LOCKED PLL not locked 0 PLL_LOCKED PLL locked 1 RESERVED Reserved 1 32 SYSRESSTAT System reset status register 0x30 read-only n 0x0 0x0 BOD Status of the Brown-out detect reset 3 4 ENUM NO_BOD_RESET_DETECTE No BOD reset detected 0 BOD_RESET_DETECTED BOD reset detected 1 EXTRST Status of the external RESET pin 1 2 ENUM NO_RESET_EVENT_DETEC No RESET event detected 0 RESET_DETECTED RESET detected 1 POR POR reset status 0 1 ENUM NO_POR_DETECTED No POR detected 0 POR_DETECTED POR detected 1 RESERVED Reserved 5 32 SYSRST Status of the software system reset. The ARM software reset has the same effect as the hardware reset using the RESET pin. 4 5 ENUM NO_SYSTEM_RESET_DETE No System reset detected 0 SYSTEM_RESET_DETECTE System reset detected 1 WDT Status of the Watchdog reset 2 3 ENUM NO_WDT_RESET_DETECTE No WDT reset detected 0 WDT_RESET_DETECTED WDT reset detected 1 SYSTCKCAL System tick counter calibration 0x154 read-write n 0x0 0x0 CAL System tick timer calibration value 0 26 RESERVED Reserved 26 32 SYSTICKCLKDIV SYSTICK clock divder 0xB0 read-write n 0x0 0x0 DIV SYSTICK clock divider values. 0: Disable SYSTICK timer clock. 1: Divide by 1. to 255: Divide by 255. 0 8 RESERVED Reserved 8 32 TRACECLKDIV ARM trace clock divider 0xAC read-write n 0x0 0x0 DIV ARM trace clock divider values. 0: Disable TRACE_CLK. 1: Divide by 1. to 255: Divide by 255. 0 8 RESERVED Reserved 8 32 UARTCLKDIV UART clock divder 0x98 read-write n 0x0 0x0 DIV UART_PCLK clock divider values 0: Disable UART_PCLK. 1: Divide by 1. to 255: Divide by 255. 0 8 RESERVED Reserved 8 32 USBCLKDIV USB clock source divider 0xC8 read-write n 0x0 0x0 DIV USB clock divider values. 0: Disable USB clock. 1: Divide by 1. to 255: Divide by 255. 0 8 RESERVED Reserved 8 32 USBCLKSEL USB clock source select 0xC0 read-write n 0x0 0x0 RESERVED Reserved 2 32 SEL USB clock source 0 2 ENUM USB_PLL_OUT USB PLL out 0x0 MAIN_CLOCK Main clock 0x1 RESERVED Reserved 0x3 RESERVED Reserved 0x3 USBCLKUEN USB clock source update enable 0xC4 read-write n 0x0 0x0 ENA Enable USB clock source update 0 1 ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved 1 32 USBPLLCLKSEL USB PLL clock source select 0x48 read-write n 0x0 0x0 RESERVED Reserved 2 32 SEL USB PLL clock source 0 2 ENUM IRC_THE_USB_PLL_CLO IRC. The USB PLL clock source must be switched to system oscillator for correct USB operation. 0x0 SYSTEM_OSCILLATOR System oscillator 0x1 RESERVED Reserved 0x3 RESERVED Reserved 0x3 USBPLLCLKUEN USB PLL clock source update enable 0x4C read-write n 0x0 0x0 ENA Enable USB PLL clock source update 0 1 ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved 1 32 USBPLLCTRL USB PLL control 0x10 read-write n 0x0 0x0 MSEL Feedback divider value. The division value M is the programmed MSEL value + 1. 00000: Division ratio M = 1 to 11111: Division ratio M = 32. 0 5 PSEL Post divider ratio P. The division ratio is 2 x P. 5 7 ENUM P_EQ_1 P = 1 0x0 P_EQ_2 P = 2 0x1 P_EQ_4 P = 4 0x2 P_EQ_8 P = 8 0x3 RESERVED Reserved. Do not write ones to reserved bits. 7 32 USBPLLSTAT USB PLL status 0x14 read-only n 0x0 0x0 LOCK PLL lock status 0 1 ENUM PLL_NOT_LOCKED PLL not locked 0 PLL_LOCKED PLL locked 1 RESERVED Reserved 1 32 WDTCLKDIV WDT clock divider 0xD8 read-write n 0x0 0x0 DIV WDT clock divider values. 0: Disable WDCLK. 1: Divide by 1. to 255: Divide by 255. 0 8 RESERVED Reserved 8 32 WDTCLKSEL WDT clock source select 0xD0 read-write n 0x0 0x0 RESERVED Reserved 2 32 SEL WDT clock source 0 2 ENUM IRC_OSCILLATOR IRC oscillator 0x0 MAIN_CLOCK Main clock 0x1 WATCHDOG_OSCILLATOR Watchdog oscillator 0x2 RESERVED Reserved 0x3 WDTCLKUEN WDT clock source update enable 0xD4 read-write n 0x0 0x0 ENA Enable WDT clock source update 0 1 ENUM NO_CHANGE No change 0 UPDATE_CLOCK_SOURCE Update clock source 1 RESERVED Reserved 1 32 WDTOSCCTRL Watchdog oscillator control 0x24 read-write n 0x0 0x0 DIVSEL Select divider for Fclkana. wdt_osc_clk = Fclkana (2 x (1 + DIVSEL)). 00000: 2 x (1 + DIVSEL) = 2 00001: 2 x (1 + DIVSEL) = 4 to 11111: 2 x (1 + DIVSEL) = 64 0 5 FREQSEL Select watchdog oscillator analog output frequency (Fclkana). 5 9 ENUM 0_5_MHZ 0.5 MHz 0x1 0_8_MHZ 0.8 MHz 0x2 1_1_MHZ 1.1 MHz 0x3 1_4_MHZ 1.4 MHz 0x4 1_6_MHZ 1.6 MHz 0x5 1_8_MHZ 1.8 MHz 0x6 2_0_MHZ 2.0 MHz 0x7 2_2_MHZ 2.2 MHz 0x8 2_4_MHZ 2.4 MHz 0x9 2_6_MHZ 2.6 MHz 0xA 2_7_MHZ 2.7 MHz 0xB 2_9_MHZ 2.9 MHz 0xC 3_1_MHZ 3.1 MHz 0xD 3_2_MHZ 3.2 MHz 0xE 3_4_MHZ 3.4 MHz 0xF RESERVED Reserved 9 32 UART UART UART 0x0 0x0 0xFFF registers n UART 46 ACR Auto-baud Control Register. Contains controls for the auto-baud feature. 0x20 read-write n 0x0 0x0 ABEOINTCLR End of auto-baud interrupt clear bit (write only accessible). 8 9 ENUM NOACTION Writing a 0 has no impact. 0 CLEAR Writing a 1 will clear the corresponding interrupt in the IIR. 1 ABTOINTCLR Auto-baud time-out interrupt clear bit (write only accessible). 9 10 ENUM NOACTION Writing a 0 has no impact. 0 CLEAR Writing a 1 will clear the corresponding interrupt in the IIR. 1 AUTORESTART Auto restart 2 3 ENUM NO_RESTART No restart 0 RESTART_IN_CASE_OF_T Restart in case of time-out (counter restarts at next UART Rx falling edge) 1 MODE Auto-baud mode select bit. 1 2 ENUM MODE_0_ Mode 0. 0 MODE_1_ Mode 1. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 10 32 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 10 32 START This bit is automatically cleared after auto-baud completion. 0 1 ENUM AUTO_BAUD_STOP_AUTO Auto-baud stop (auto-baud is not running). 0 AUTO_BAUD_START_AUT Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion. 1 DLL Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. When DLAB=1. RBR 0x0 read-write n 0x0 0x0 DLLSB The UART Divisor Latch LSB Register, along with the DLM register, determines the baud rate of the UART. 0 8 RESERVED Reserved 8 32 DLM Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. When DLAB=1. 0x4 read-write n 0x0 0x0 DLMSB The UART Divisor Latch MSB Register, along with the DLL register, determines the baud rate of the UART. 0 8 RESERVED Reserved 8 32 FCR FIFO Control Register. Controls UART FIFO usage and modes. IIR 0x8 write-only n 0x0 0x0 FIFOEN FIFO Enable 0 1 ENUM DISABLED UART FIFOs are disabled. Must not be used in the application. 0 ENABLED Active high enable for both UART Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the UART FIFOs. 1 RESERVED Reserved 8 32 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 6 RESERVED Reserved 8 32 RXFIFOR RX FIFO Reset 1 2 ENUM NOACTION No impact on either of UART FIFOs. 0 CLEAR Writing a logic 1 to FCR[1] will clear all bytes in UART Rx FIFO, reset the pointer logic. This bit is self-clearing. 1 RXTLVL RX Trigger Level. These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated. 6 8 ENUM TRIGGER_LEVEL_0_1_C Trigger level 0 (1 character or 0x01). 0x0 TRIGGER_LEVEL_1_4_C Trigger level 1 (4 characters or 0x04). 0x1 TRIGGER_LEVEL_2_8_C Trigger level 2 (8 characters or 0x08). 0x2 TRIGGER_LEVEL_3_14_ Trigger level 3 (14 characters or 0x0E). 0x3 TXFIFOR TX FIFO Reset 2 3 ENUM NOACTION No impact on either of UART FIFOs. 0 CLEAR Writing a logic 1 to FCR[2] will clear all bytes in UART TX FIFO, reset the pointer logic. This bit is self-clearing. 1 FDR Fractional Divider Register. Generates a clock input for the baud rate divider. 0x28 read-write n 0x0 0x0 DIVADDVAL Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART baud rate. 0 4 MULVAL Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART to operate properly, regardless of whether the fractional baud rate generator is used or not. 4 8 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 8 32 IER Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. When DLAB=0. DLM 0x4 read-write n 0x0 0x0 ABEOINTEN Enables the end of auto-baud interrupt. 8 9 ENUM DISABLE Disable end of auto-baud Interrupt. 0 ENABLE Enable end of auto-baud Interrupt. 1 ABTOINTEN Enables the auto-baud time-out interrupt. 9 10 ENUM DISABLE Disable auto-baud time-out Interrupt. 0 ENABLE Enable auto-baud time-out Interrupt. 1 RBRIE Interrupt Enable. Enables the Receive Data Available interrupt for UART. It also controls the Character Receive Time-out interrupt. 0 1 ENUM DISABLE Disable the RDA interrupt. 0 ENABLE Enable the RDA interrupt. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 10 32 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 4 7 RESERVED Reserved 7 8 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 10 32 RXLIE Line Interrupt Enable. Enables the UART RX line status interrupts. The status of this interrupt can be read from LSR[4:1]. 2 3 ENUM DISABLE Disable the RX line status interrupts. 0 ENABLE Enable the RX line status interrupts. 1 THREIE Interrupt Enable. Enables the THRE interrupt for UART. The status of this interrupt can be read from LSR[5]. 1 2 ENUM DISABLE Disable the THRE interrupt. 0 ENABLE Enable the THRE interrupt. 1 IIR Interrupt ID Register. Identifies which interrupt(s) are pending. 0x8 read-only n 0x0 0x0 ABEOINT End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled. 8 9 ABTOINT Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled. 9 10 FIFOEN These bits are equivalent to FCR[0]. 6 8 INTID Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART Rx FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111). 1 4 ENUM MODEM 4 - Modem interrupt. 0x0 THRE 3 - THRE Interrupt. 0x1 RDA 2a - Receive Data Available (RDA). 0x2 RECEIVE 1 - Receive Line Status (RLS). 0x3 CTIMEOUT 2b - Character Time-out Indicator (CTI). 0x6 INTSTATUS Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1]. 0 1 ENUM INT At least one interrupt is pending. 0 NOINT No interrupt is pending. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 10 32 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 10 32 LCR Line Control Register. Contains controls for frame formatting and break generation. 0xC read-write n 0x0 0x0 BC Break Control 6 7 ENUM DISABLE_BREAK_TRANSM Disable break transmission. 0 ENABLE_BREAK_TRANSMI Enable break transmission. Output pin UART TXD is forced to logic 0 when LCR[6] is active high. 1 DLAB Divisor Latch Access Bit (DLAB) 7 8 ENUM DISABLE_ACCESS_TO_DI Disable access to Divisor Latches. 0 ENABLE_ACCESS_TO_DIV Enable access to Divisor Latches. 1 PE Parity Enable 3 4 ENUM DISABLE_PARITY_GENER Disable parity generation and checking. 0 ENABLE_PARITY_GENERA Enable parity generation and checking. 1 PS Parity Select 4 6 ENUM ODD_PARITY_NUMBER_O Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd. 0x0 EVEN_PARITY_NUMBER_ Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even. 0x1 FORCED_1_STICK_PARIT Forced 1 stick parity. 0x2 FORCED_0_STICK_PARIT Forced 0 stick parity. 0x3 RESERVED Reserved 8 32 SBS Stop Bit Select 2 3 ENUM 1_STOP_BIT_ 1 stop bit. 0 2_STOP_BITS_1_5_IF_ 2 stop bits (1.5 if LCR[1:0]=00). 1 WLS Word Length Select 0 2 ENUM 5_BIT_CHARACTER_LENG 5-bit character length. 0x0 6_BIT_CHARACTER_LENG 6-bit character length. 0x1 7_BIT_CHARACTER_LENG 7-bit character length. 0x2 8_BIT_CHARACTER_LENG 8-bit character length. 0x3 LSR Line Status Register. Contains flags for transmit and receive status, including line errors. 0x14 read-only n 0x0 0x0 modify BI Break Interrupt. When RXD1 is held in the spacing state (all zeros) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). A LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART RBR FIFO. 4 5 ENUM INACTIVE Break interrupt status is inactive. 0 ACTIVE Break interrupt status is active. 1 FE Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. A LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to re-synchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART RBR FIFO. 3 4 ENUM INACTIVE Framing error status is inactive. 0 ACTIVE Framing error status is active. 1 OE Overrun Error. The overrun error condition is set as soon as it occurs. A LSR read clears LSR[1]. LSR[1] is set when UART RSR has a new character assembled and the UART RBR FIFO is full. In this case, the UART RBR FIFO will not be overwritten and the character in the UART RSR will be lost. 1 2 ENUM INACTIVE Overrun error status is inactive. 0 ACTIVE Overrun error status is active. 1 PE Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. A LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART RBR FIFO. 2 3 ENUM INACTIVE Parity error status is inactive. 0 ACTIVE Parity error status is active. 1 RDR Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART RBR FIFO is empty. 0 1 ENUM RBR_IS_EMPTY_ RBR is empty. 0 RBR_CONTAINS_VALID RBR contains valid data. 1 RESERVED Reserved 8 32 RXFE Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART FIFO. 7 8 ENUM NOERROR RBR contains no UART RX errors or FCR[0]=0. 0 ERRORS UART RBR contains at least one UART RX error. 1 TEMT Transmitter Empty. TEMT is set when both THR and TSR are empty TEMT is cleared when either the TSR or the THR contain valid data. 6 7 ENUM VALID THR and/or the TSR contains valid data. 0 EMPTY THR and the TSR are empty. 1 THRE Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART THR and is cleared on a THR write. 5 6 ENUM VALID THR contains valid data. 0 EMPTY THR is empty. 1 MCR Modem control register 0x10 read-write n 0x0 0x0 CTSEN CTS enable 7 8 ENUM DISABLE_AUTO_CTS_FLO Disable auto-cts flow control. 0 ENABLE_AUTO_CTS_FLOW Enable auto-cts flow control. 1 DTRCTRL Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active. 0 1 LMS Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD, has no effect on loopback and output pin, TXD is held in marking state. The four modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the four modem outputs are connected to the four modem inputs. As a result of these connections, the upper four bits of the MSR will be driven by the lower four bits of the MCR rather than the four modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower four bits of MCR. 4 5 RESERVED Reserved 8 32 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 5 6 RESERVED Reserved 8 32 RTSCTRL Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active. 1 2 RTSEN RTS enable 6 7 ENUM DISABLE_AUTO_RTS_FLO Disable auto-rts flow control. 0 ENABLE_AUTO_RTS_FLOW Enable auto-rts flow control. 1 MSR Modem status register 0x18 read-only n 0x0 0x0 modify CTS Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode. 4 5 DCD Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode. 7 8 DELTACTS Set upon state change of input CTS. Cleared on a MSR read. 0 1 ENUM NO_STATE_CHANGE No change detected on modem input CTS. 0 STATE_CHANGE_DETECTE State change detected on modem input CTS. 1 DELTADCD Set upon state change of input DCD. Cleared on a MSR read. 3 4 ENUM NO_STATE_CHANGE No change detected on modem input DCD. 0 STATE_CHANGE_DETECTE State change detected on modem input DCD. 1 DELTADSR Set upon state change of input DSR. Cleared on a MSR read. 1 2 ENUM NO_STATE_CHANGE No change detected on modem input DSR. 0 STATE_CHANGE_DETECTE State change detected on modem input DSR. 1 DSR Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode. 5 6 RESERVED Reserved 8 32 RI Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode. 6 7 TERI Trailing Edge RI. Set upon low to high transition of input RI. Cleared on a MSR read. 2 3 ENUM NO_STATE_CHANGE No change detected on modem input, RI. 0 LOW_TO_HIGH_TRANSITI Low-to-high transition detected on RI. 1 RBR Receiver Buffer Register. Contains the next received character to be read. When DLAB=0. 0x0 read-only n 0x0 0x0 RBR The UART Receiver Buffer Register contains the oldest received byte in the UART RX FIFO. 0 8 RESERVED Reserved 8 32 RS485ADRMATCH RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. 0x50 read-write n 0x0 0x0 ADRMATCH Contains the address match value. 0 8 RESERVED Reserved 8 32 RS485CTRL RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. 0x4C read-write n 0x0 0x0 AADEN AAD enable 2 3 ENUM DISABLED Auto Address Detect (AAD) is disabled. 0 ENABLED Auto Address Detect (AAD) is enabled. 1 DCTRL Direction control enable 4 5 ENUM DISABLE_AUTO_DIRECTI Disable Auto Direction Control. 0 ENABLE_AUTO_DIRECTIO Enable Auto Direction Control. 1 NMMEN NMM enable 0 1 ENUM DISABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled. 0 ENABLED RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt. 1 OINV This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 5 6 ENUM LOW The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted. 0 HIGH The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 6 32 RXDIS Receiver enable 1 2 ENUM ENABLED The receiver is enabled. 0 DISABLED The receiver is disabled. 1 SEL Direction control pins select 3 4 ENUM RTS If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control. 0 DTR If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control. 1 RS485DLY RS-485/EIA-485 direction control delay. 0x54 read-write n 0x0 0x0 DLY Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter. 0 8 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 8 32 SCR Scratch Pad Register. Eight-bit temporary storage for software. 0x1C read-write n 0x0 0x0 Pad A readable, writable byte. 0 8 RESERVED Reserved 8 32 TER Transmit Enable Register. Turns off UART transmitter for use with software flow control. 0x30 read-write n 0x0 0x0 RESERVED Reserved 8 32 RESERVED Reserved 8 32 TXEN When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character. 7 8 THR Transmit Holding Register. The next character to be transmitted is written here. When DLAB=0. RBR 0x0 write-only n 0x0 0x0 modify RESERVED Reserved 8 32 THR Writing to the UART Transmit Holding Register causes the data to be stored in the UART transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available. 0 8 USB USB device USB 0x0 0x0 0xFFF registers n USBIRQ 47 USB 47 USBFIQ 48 CMDCODE USB Command Code 0x10 write-only n 0x0 0x0 CMD_PHASE Command phase action 8 16 ENUM WRITE Write 0x01 READ Read 0x02 COMMAND Command 0x05 CODE_WDATA This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA). 16 24 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 24 32 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 24 32 CMDDATA USB Command Data 0x14 read-only n 0x0 0x0 CMD_RDATA Command Read Data. 0 8 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 8 32 CTRL USB Control 0x28 read-write n 0x0 0x0 LOG_ENDPOINT Logical Endpoint number. 2 6 RD_EN Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData. 0 1 ENUM READ_MODE_IS_DISABLE Read mode is disabled. 0 READ_MODE_IS_ENABLED Read mode is enabled. 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 6 32 WR_EN Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent. 1 2 ENUM WRITE_MODE_IS_DISABL Write mode is disabled. 0 WRITE_MODE_IS_ENABLE Write mode is enabled. 1 DEVFIQSEL USB Device FIQ select 0x2C write-only n 0x0 0x0 BULKIN Interrupt routing for bulk in endpoints For logical endpoint 3 (physical endpoints 6 and 7) only. 2 3 ENUM LOWPRIORITY BULKIN interrupt will be routed to the low-priority interrupt line IRQ. 0 HIGHPRIORITY BULKIN interrupt will be routed to the high-priority interrupt line FIQ. 1 BULKOUT Interrupt routing for bulk out endpoints For logical endpoint 3 (physical endpoints 6 and 7) only. 1 2 ENUM LOWPRIORITY BULKOUT interrupt will be routed to the low-priority interrupt line IRQ. 0 HIGHPRIORITY BULKOUT interrupt will be routed to the high-priority interrupt line FIQ. 1 FRAME This interrupt comes from a 1 KHz free running clock resynchronized on the incoming SoF tokens. This is to be used for isochronous packet transfer. 0 1 ENUM LOWPRIORITY FRAME interrupt will be routed to the low-priority interrupt line IRQ. 0 HIGHPRIORITY FRAME interrupt will be routed to the high-priority interrupt line FIQ. 1 RESERVED Reserved 3 32 DEVINTCTRL USB Device Interrupt Clear 0x8 write-only n 0x0 0x0 CC_EMPTY_CLR The command code register (USBCmdCode) is empty (New command can be written). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 10 11 CD_FULL_CLR Command data register (USBCmdData) is full (Data can be read now). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 11 12 DEV_STAT_CLR Set when USB Bus reset, USB suspend change, or Connect change event occurs. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 9 10 EP0_CLR USB core interrupt for physical endpoint 0. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 1 2 EP1_CLR USB core interrupt for physical endpoint 1. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 2 3 EP2_CLR USB core interrupt for physical endpoint 2. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 3 4 EP3_CLR USB core interrupt for physical endpoint 3. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 4 5 EP4_CLR USB core interrupt for physical endpoint 4. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 5 6 EP5_CLR USB core interrupt for physical endpoint 5. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 6 7 EP6_CLR USB core interrupt for physical endpoint 6. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 7 8 EP7_CLR USB core interrupt for physical endpoint 7. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 8 9 FRAME_CLR Frame interrupt . For isochronous packet transfers. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 0 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 14 32 RXENDPKT_CLR The current packet in the endpoint buffer is transferred to the CPU. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 12 13 TXENDPKT_CLR The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared. 13 14 DEVINTEN USB Device Interrupt Enable 0x4 read-write n 0x0 0x0 CC_EMPTY_EN The command code register (USBCmdCode) is empty (New command can be written). 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set. 10 11 CD_FULL_EN Command data register (USBCmdData) is full (Data can be read now). 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set. 11 12 DEV_STAT_EN Set when USB Bus reset, USB suspend change, or Connect change event occurs. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set. 9 10 EP0_EN USB core interrupt for physical endpoint 0. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set. 1 2 EP1_EN USB core interrupt for physical endpoint 1. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set. 2 3 EP2_EN USB core interrupt for physical endpoint 2. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set. 3 4 EP3_EN USB core interrupt for physical endpoint 3. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set. 4 5 EP4_EN USB core interrupt for physical endpoint 4. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set. 5 6 EP5_EN USB core interrupt for physical endpoint 5. 0 = no interrupt. 1 = interrupt pending. 6 7 EP6_EN USB core interrupt for physical endpoint 6. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set. 7 8 EP7_EN USB core interrupt for physical endpoint 7. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set. 8 9 FRAME_EN Frame interrupt . For isochronous packet transfers. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set. 0 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 14 32 RXENDPKT_EN The current packet in the endpoint buffer is transferred to the CPU. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set. 12 13 TXENDPKT_EN The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set. 13 14 DEVINTSET USB Device Interrupt Set 0xC write-only n 0x0 0x0 CC_EMPTY_SET The command code register (USBCmdCode) is empty (New command can be written). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 10 11 CD_FULL_SET Command data register (USBCmdData) is full (Data can be read now). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 11 12 DEV_STAT_SET Set when USB Bus reset, USB suspend change, or Connect change event occurs. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 9 10 EP0_SET USB core interrupt for physical endpoint 0. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 1 2 EP1_SET USB core interrupt for physical endpoint 1. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 2 3 EP2_SET USB core interrupt for physical endpoint 2. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 3 4 EP3_SET USB core interrupt for physical endpoint 3. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 4 5 EP4_SET USB core interrupt for physical endpoint 4. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 5 6 EP5_SET USB core interrupt for physical endpoint 5. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 6 7 EP6_SET USB core interrupt for physical endpoint 6. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 7 8 EP7_SET USB core interrupt for physical endpoint 7. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 8 9 FRAME_SET Frame interrupt . For isochronous packet transfers. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 0 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 14 32 RXENDPKT_SET The current packet in the endpoint buffer is transferred to the CPU. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 12 13 TXENDPKT_SET The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set. 13 14 DEVINTST USB Device Interrupt Status 0x0 read-only n 0x0 0x0 CC_EMPTY The command code register (USBCmdCode) is empty (New command can be written). 0 = no interrupt. 1 = interrupt pending. 10 11 CD_FULL Command data register (USBCmdData) is full (Data can be read now). 0 = no interrupt. 1 = interrupt pending. 11 12 DEV_STAT Set when USB Bus reset, USB suspend change, or Connect change event occurs. Refer to Section 10.11.7. 0 = no interrupt. 1 = interrupt pending. 9 10 EP0 USB core interrupt for physical endpoint 0. 0 = no interrupt. 1 = interrupt pending. 1 2 EP1 USB core interrupt for physical endpoint 1. 0 = no interrupt. 1 = interrupt pending. 2 3 EP2 USB core interrupt for physical endpoint 2. 0 = no interrupt. 1 = interrupt pending. 3 4 EP3 USB core interrupt for physical endpoint 3. 0 = no interrupt. 1 = interrupt pending. 4 5 EP4 USB core interrupt for physical endpoint 4. 0 = no interrupt. 1 = interrupt pending. 5 6 EP5 USB core interrupt for physical endpoint 5. 0 = no interrupt. 1 = interrupt pending. 6 7 EP6 USB core interrupt for physical endpoint 6. 0 = no interrupt. 1 = interrupt pending. 7 8 EP7 USB core interrupt for physical endpoint 7. 0 = no interrupt. 1 = interrupt pending. 8 9 FRAME The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. 0 = no interrupt. 1 = interrupt pending. 0 1 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 14 32 RxENDPKT The current packet in the endpoint buffer is transferred to the CPU. 0 = no interrupt. 1 = interrupt pending. 12 13 TxENDPKT The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen). 0 = no interrupt. 1 = interrupt pending. 13 14 RXDATA USB Receive Data 0x18 read-only n 0x0 0x0 RX_DATA Data received. 0 32 RXPLEN USB Receive Packet Length 0x20 read-only n 0x0 0x0 DV Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet. 10 11 ENUM DATA_IS_INVALID_ Data is invalid. 0 DATA_IS_VALID_ Data is valid. 1 PKT_LNGTH The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt. 0 10 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 11 32 TXDATA USB Transmit Data 0x1C write-only n 0x0 0x0 TX_DATA Transmit Data. 0 32 TXPLENn USB Transmit Packet Length 0x24 write-only n 0x0 0x0 PKT_LNGTH The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt. 0 10 RESERVED Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. 10 32 WWDT Windowed WatchDog Timer (WWDT) WWDT 0x0 0x0 0xFFF registers n WDT 50 FEED Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC. 0x8 write-only n 0x0 0x0 Feed Feed value should be 0xAA followed by 0x55. 0 8 RESERVED Reserved 8 32 MOD Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. 0x0 read-write n 0x0 0x0 RESERVED Reserved. Read value is undefined, only zero should be written. 5 32 WDEN Watchdog enable bit. This bit is Set Only. Remark: Setting this bit to one also locks the watchdog clock source. Once the watchdog timer is enabled, the watchdog timer clock source cannot be changed. If the watchdog timer is needed in Deep-sleep mode, the watchdog clock source must be changed to watchdog oscillator before setting this bit to one. 0 1 ENUM STOP The watchdog timer is stopped. 0 RUN The watchdog timer is running. 1 WDINT Watchdog interrupt flag. Set when the timer reaches the value in WDWARNINT. Cleared by software. 3 4 WDPROTECT Watchdog update mode. This bit is Set Only. 4 5 ENUM ANYTIME The watchdog reload value (WDTC) can be changed at any time. 0 MATCH The watchdog reload value (WDTC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. Note: this mode is intended for use only when WDRESET =1. 1 WDRESET Watchdog reset enable bit. This bit is Set Only. 1 2 ENUM RESET A watchdog timeout will not cause a chip reset. 0 INTERRUPT A watchdog timeout will cause a chip reset. 1 WDTOF Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by events associated with WDPROTECT, cleared by software. Causes a chip reset if WDRESET = 1. 2 3 TC Watchdog timer constant register. This register determines the time-out value. 0x4 read-write n 0x0 0x0 Count Watchdog time-out interval. 0 24 RESERVED Reserved. Read value is undefined, only zero should be written. 24 32 TV Watchdog timer value register. This register reads out the current value of the Watchdog timer. 0xC read-only n 0x0 0x0 Count Counter timer value. 0 24 RESERVED Reserved. Read value is undefined, only zero should be written. 24 32 WARNINT Watchdog Warning Interrupt compare value. 0x14 read-write n 0x0 0x0 RESERVED Reserved. Read value is undefined, only zero should be written. 10 32 WARNINT Watchdog warning interrupt compare value. 0 10 WINDOW Watchdog Window compare value. 0x18 read-write n 0x0 0x0 RESERVED Reserved. Read value is undefined, only zero should be written. 24 32 WINDOW Watchdog window value. 0 24